Re: [PATCH 0/2] PCI/ASPM: Avoid L0s and L1 on Sophgo 2042/2044 PCIe Root Ports

[Chen Wang]

On 12/27/2025 12:30 AM, Bjorn Helgaas wrote:
> On Thu, Dec 25, 2025 at 06:05:27PM +0800, Inochi Amaoto wrote:
> > Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM
> > states for devicetree platforms") force enable ASPM on all device tree
> > platform, the SG2042/SG2044 PCIe Root Ports breaks as it advertises L0s
> > and L1 capabilities without supporting it.
> >
> > Override the L0s and L1 Support advertised in Link Capabilities by the
> > SG2042/SG2044 Root Ports so we don't try to enable those states.
> >
> > Inochi Amaoto (2):
> >    PCI/ASPM: Avoid L0s and L1 on Sophgo 2042 PCIe [1f1c:2042] Root Ports
> >    PCI/ASPM: Avoid L0s and L1 on Sophgo 2044 PCIe [1f1c:2044] Root Ports
> >
> >   drivers/pci/quirks.c    | 2 ++
> >   include/linux/pci_ids.h | 2 ++
> >   2 files changed, 4 insertions(+)
> 1) Can somebody at Sophgo confirm that this is a hardware erratum?  I
> just want to make rule out some kind of OS bug in configuring L0s/L1.
>
> 2) Why don't we have a MAINTAINERS entry for this driver?  I failed to
> notice that the series we applied
> (https://lore.kernel.org/all/cover.1757643388.git.unicorn_wang@xxxxxxxxxxx/)
> does not include a maintainer.  Chen, since you posted that series,
> are you willing to sign up to maintain it?
Sorry, I didn't realize I needed to submit maintainer information 
separately for each driver when I submitted the PCIe driver code.

Yes, I will be maintaining the SG2042 PCIe driver. Do I need to add an 
entry to the MAINTAINERS file?

Chen

> Bjorn