Re: [PATCH V1 3/4] arm64: dts: qcom: hamoa: Add UFS nodes for hamoa SoC

[Pradeep Pragallapati]

On 12/29/2025 5:45 PM, Konrad Dybcio wrote:
> On 12/29/25 7:06 AM, Pradeep P V K wrote:
> > Add UFS host controller and PHY nodes for hamoa SoC.
> >
> > Signed-off-by: Pradeep P V K <pradeep.pragallapati@xxxxxxxxxxxxxxxx>
> > ---
> >   arch/arm64/boot/dts/qcom/hamoa.dtsi | 119 +++++++++++++++++++++++++++-
> >   1 file changed, 118 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
> > index bb7c14d473c9..340b907657be 100644
> > --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
> > @@ -834,7 +834,10 @@ gcc: clock-controller@100000 {
> >   				 <0>,
> >   				 <0>,
> >   				 <0>,
> > -				 <0>;
> > +				 <0>,
> > +				 <&ufs_mem_phy 0>,
> > +				 <&ufs_mem_phy 1>,
> > +				 <&ufs_mem_phy 2>;
> This patch cannot be applied as-is (needs GCC bindings changes first)
> which you didn't mention in the cover letter.
>
> If it were picked up, we'd get DTB valdation errors.
ok, i will mention the link to GCC postings in my cover letter in my 
next patchset.
> >   
> >   			power-domains = <&rpmhpd RPMHPD_CX>;
> >   			#clock-cells = <1>;
> > @@ -3845,6 +3848,120 @@ pcie4_phy: phy@1c0e000 {
> >   			status = "disabled";
> >   		};
> >   
> > +		ufs_mem_phy: phy@1d80000 {
> > +			compatible = "qcom,hamoa-qmp-ufs-phy", "qcom,sm8550-qmp-ufs-phy";
> > +			reg = <0x0 0x1d80000 0x0 0x2000>;
> Please pad the address part to 8 hex digits, so 0x1d80000 -> 0x01d80000
>
> [...]
ack. i will update in my next patchset.
> > +		ufs_mem_hc: ufs@1d84000 {
> > +			compatible = "qcom,hamoa-ufshc", "qcom,sm8550-ufshc", "qcom,ufshc",
> > +				     "jedec,ufs-2.0";
> 1 a line would be neater, perhaps in the node above too
sure, will update in my next patchset.
> > +			reg = <0x0 0x1d84000 0x0 0x3000>;
> Similar case as before
ack. will update in my next patchset.
> lgtm otherwise
>
> Konrad