Re: [PATCH v2] PCI: loongson: Override PCIe bridge supported speeds for older Loongson 3C6000 series steppings

[Huacai Chen]

On Sun, Jan 4, 2026 at 7:03 PM Mingcong Bai <jeffbai@xxxxxxx> wrote:
>
> Hi Ziyao Li,
>
> 在 2026/1/4 18:00, Ziyao Li via B4 Relay 写道:
> > From: Ziyao Li <liziyao@xxxxxxxxxxxxx>
> >
> > Older steppings of the Loongson 3C6000 series incorrectly report the
> > supported link speeds on their PCIe bridges (device IDs 3c19, 3c29) as
> > only 2.5 GT/s, despite the upstream bus supporting speeds from 2.5 GT/s
> > up to 16 GT/s.
> >
> > As a result, certain PCIe devices would be incorrectly probed as a Gen1-
> > only, even if higher link speeds are supported, harming performance and
> > prevents dynamic link speed functionality from being enabled in drivers
> > such as amdgpu.
> >
> > Manually override the `supported_speeds` field for affected PCIe bridges
> > with those found on the upstream bus to correctly reflect the supported
> > link speeds.
> >
> > This patch was originally found from AOSC OS[1].
>
> Thanks for the patch. Looping loongarch.
I prefer naming consistency, which means loongson_pci_bridge_speed_quirk().

Huacai
>
> Best Regards,
> Mingcong Bai
>