Re: [PATCH RFC] arm64: dts: qcom: x1e80100: Fix USB combo PHYs SS1 and SS2 ref clocks

[Bjorn Andersson]

On Mon, 03 Nov 2025 18:51:40 +0200, Abel Vesa wrote:
> It seems the USB combo SS1 and SS2 ref clocks have another gate, unlike
> the SS0. These gates are part of the TCSR clock controller.
> 
> At least on Dell XPS 13 (9345), if the ref clock provided by the TCSR
> clock controller for SS1 PHY is disabled on the clk_disable_unused late
> initcall, the PHY fails to initialize. It doesn't happen on the SS0 PHY
> and the SS2 is not used on this device.
> 
> [...]

Applied, thanks!

[1/1] arm64: dts: qcom: x1e80100: Fix USB combo PHYs SS1 and SS2 ref clocks
      commit: 3af51501e2b8c87564b5cda43b0e5c316cf54717

Best regards,
-- 
Bjorn Andersson <andersson@xxxxxxxxxx>