Re: [PATCH v2 2/4] arm64: dts: qcom: talos: Add CCI definitions
From: Dmitry Baryshkov
Date: Tue Jan 06 2026 - 13:27:57 EST
On Tue, Jan 06, 2026 at 05:39:54PM +0800, Wenmeng Liu wrote:
> Qualcomm Talos SoC contains single controller,
> containing 2 I2C hosts.
>
> Signed-off-by: Wenmeng Liu <wenmeng.liu@xxxxxxxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/talos.dtsi | 72 +++++++++++++++++++++++++++++++++++++
> 1 file changed, 72 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi
> index e1dfaff9b6bf8641b19a685e74d60ad4e1e99d41..461a39968d928260828993ff3549aa15fd1870df 100644
> --- a/arch/arm64/boot/dts/qcom/talos.dtsi
> +++ b/arch/arm64/boot/dts/qcom/talos.dtsi
> @@ -1549,6 +1549,42 @@ tlmm: pinctrl@3100000 {
> #interrupt-cells = <2>;
> wakeup-parent = <&pdc>;
>
> + cci_default: cci0-default-state {
> + cci_i2c0_default: cci-i2c0-default-pins {
These need to be split, having just one host per state.
> + /* SDA, SCL */
> + pins = "gpio32", "gpio33";
> + function = "cci_i2c";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + cci_i2c1_default: cci-i2c1-default-pins {
> + /* SDA, SCL */
> + pins = "gpio34", "gpio35";
> + function = "cci_i2c";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> +
> + cci_sleep: cci-sleep-state {
> + cci_i2c0_sleep: cci-i2c0-sleep-state {
The same
> + /* SDA, SCL */
> + pins = "gpio32", "gpio33";
> + function = "cci_i2c";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + cci_i2c1_sleep: cci-i2c1-sleep-state {
> + /* SDA, SCL */
> + pins = "gpio34", "gpio35";
> + function = "cci_i2c";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> + };
> +
> qup_i2c1_data_clk: qup-i2c1-data-clk-state {
> pins = "gpio4", "gpio5";
> function = "qup0";
> @@ -3785,6 +3821,42 @@ videocc: clock-controller@ab00000 {
> #power-domain-cells = <1>;
> };
>
> + cci: cci@ac4a000 {
> + compatible = "qcom,sm6150-cci", "qcom,msm8996-cci";
> +
> + reg = <0x0 0x0ac4a000 0x0 0x4000>;
Extra double space.
> + interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
> + power-domains = <&camcc TITAN_TOP_GDSC>;
> + clocks = <&camcc CAM_CC_SOC_AHB_CLK>,
> + <&camcc CAM_CC_CPAS_AHB_CLK>,
> + <&camcc CAM_CC_CCI_CLK>;
> + clock-names = "soc_ahb",
> + "cpas_ahb",
> + "cci";
> + pinctrl-0 = <&cci_default>;
> + pinctrl-1 = <&cci_sleep>;
> + pinctrl-names = "default", "sleep";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + status = "disabled";
> +
> + cci_i2c0: i2c-bus@0 {
> + reg = <0>;
> + clock-frequency = <1000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + cci_i2c1: i2c-bus@1 {
> + reg = <1>;
> + clock-frequency = <1000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> camss: isp@acb3000 {
> compatible = "qcom,sm6150-camss";
>
>
> --
> 2.34.1
>
--
With best wishes
Dmitry