RE: [PATCH v3 5/9] thermal: renesas: rzg3e: add support for RZ/T2H and RZ/N2H

[John Madieu]

Hi Cosmin,

Thanks for your patch.

> -----Original Message-----
> From: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@xxxxxxxxxxx>
> Sent: Wednesday, November 26, 2025 2:04 PM
> To: John Madieu <john.madieu.xa@xxxxxxxxxxxxxx>; Rafael J . Wysocki
> <rafael@xxxxxxxxxx>; Daniel Lezcano <daniel.lezcano@xxxxxxxxxx>; Zhang Rui
> <rui.zhang@xxxxxxxxx>; Lukasz Luba <lukasz.luba@xxxxxxx>; Rob Herring
> <robh@xxxxxxxxxx>; Krzysztof Kozlowski <krzk+dt@xxxxxxxxxx>; Conor Dooley
> <conor+dt@xxxxxxxxxx>; Geert Uytterhoeven <geert+renesas@xxxxxxxxx>;
> magnus.damm <magnus.damm@xxxxxxxxx>; Philipp Zabel
> <p.zabel@xxxxxxxxxxxxxx>
> Cc: linux-pm@xxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx; linux-
> kernel@xxxxxxxxxxxxxxx; linux-renesas-soc@xxxxxxxxxxxxxxx; Cosmin-Gabriel
> Tanislav <cosmin-gabriel.tanislav.xa@xxxxxxxxxxx>
> Subject: [PATCH v3 5/9] thermal: renesas: rzg3e: add support for RZ/T2H
> and RZ/N2H
> 
> The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs expose the
> temperature calibration via SMC SIP and do not have a reset for the TSU
> peripheral, and use different minimum and maximum temperature values
> compared to the already supported RZ/G3E.
> 
> Although the calibration data is stored in an OTP memory, the OTP itself
> is not memory-mapped, access to it is done through an OTP controller.
> 
> The OTP controller is only accessible from the secure world, but the
> temperature calibration data stored in the OTP is exposed via SMC.
> 
> Add support for retrieving the calibration data using arm_smcc_smc().
> 
> Add a compatible for RZ/T2H, RZ/N2H can use it as a fallback.
> 
> Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@xxxxxxxxxxx>
> ---
> V3:
>  * no changes
> 
> V2:
>  * no changes
> 
>  drivers/thermal/renesas/rzg3e_thermal.c | 26 +++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
> 
> diff --git a/drivers/thermal/renesas/rzg3e_thermal.c
> b/drivers/thermal/renesas/rzg3e_thermal.c
> index d2525ad3ffcc..efd09c35b216 100644
> --- a/drivers/thermal/renesas/rzg3e_thermal.c
> +++ b/drivers/thermal/renesas/rzg3e_thermal.c
> @@ -72,6 +72,10 @@
> 
>  #define TSU_TEMP_MASK		GENMASK(11, 0)
> 
> +#define RZ_SIP_SVC_GET_SYSTSU	0x82000022
> +#define OTP_TSU_REG_ADR_TEMPHI	0x01DC
> +#define OTP_TSU_REG_ADR_TEMPLO	0x01DD
> +
>  struct rzg3e_thermal_priv;
> 
>  struct rzg3e_thermal_info {
> @@ -381,6 +385,21 @@ static int rzg3e_thermal_get_syscon_trim(struct
> rzg3e_thermal_priv *priv)
>  	return 0;
>  }
> 
> +static int rzg3e_thermal_get_smc_trim(struct rzg3e_thermal_priv *priv)
> +{
> +	struct arm_smccc_res local_res;
> +
> +	arm_smccc_smc(RZ_SIP_SVC_GET_SYSTSU, OTP_TSU_REG_ADR_TEMPLO,
> +		      0, 0, 0, 0, 0, 0, &local_res);
> +	priv->trmval0 = local_res.a0 & TSU_TEMP_MASK;
> +
> +	arm_smccc_smc(RZ_SIP_SVC_GET_SYSTSU, OTP_TSU_REG_ADR_TEMPHI,
> +		      0, 0, 0, 0, 0, 0, &local_res);
> +	priv->trmval1 = local_res.a0 & TSU_TEMP_MASK;
> +
> +	return 0;
> +}
> +
>  static int rzg3e_thermal_probe(struct platform_device *pdev)  {
>  	struct device *dev = &pdev->dev;
> @@ -539,8 +558,15 @@ static const struct rzg3e_thermal_info
> rzg3e_thermal_info = {
>  	.temp_e_mc = 126000,
>  };
> 
> +static const struct rzg3e_thermal_info rzt2h_thermal_info = {
> +	.get_trim = rzg3e_thermal_get_smc_trim,
> +	.temp_d_mc = -40000,
> +	.temp_e_mc = 125000,
> +};
> +
>  static const struct of_device_id rzg3e_thermal_dt_ids[] = {
>  	{ .compatible = "renesas,r9a09g047-tsu", .data = &rzg3e_thermal_info
> },
> +	{ .compatible = "renesas,r9a09g077-tsu", .data = &rzt2h_thermal_info
> +},
>  	{ /* sentinel */ }
>  };
>  MODULE_DEVICE_TABLE(of, rzg3e_thermal_dt_ids);
> --
> 2.52.0

Reviewed-by: John Madieu <john.madieu.xa@xxxxxxxxxxxxxx>
Tested-by: John Madieu <john.madieu.xa@xxxxxxxxxxxxxx>