Re: [PATCH v4 11/31] clk: at91: clk-usb: add support for clk_parent_data
From: Claudiu Beznea
Date: Sat Jan 10 2026 - 10:03:23 EST
Hi, Ryan,
Sorry for the late reply, I was off for a while.
On 1/5/26 19:58, Ryan.Wanner@xxxxxxxxxxxxx wrote:
On 12/23/25 07:00, claudiu beznea wrote:Because this is the only clock that uses clk_hw for all of its parents.
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On 12/18/25 18:23, Ryan.Wanner@xxxxxxxxxxxxx wrote:
On 10/20/25 12:17, Claudiu Beznea wrote:
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Hi, Ryan,
On 9/19/25 00:15, Ryan.Wanner@xxxxxxxxxxxxx wrote:
From: Claudiu Beznea <claudiu.beznea@xxxxxxxxx>
Add support for clk_parent_data in usb clock driver.
All the SoC based drivers that rely on clk-usb were adapted
to the new API change. The switch itself for SoCs will be done
in subsequent patches.
Remove the use of __clk_get_hw() for the slow clocks.
Signed-off-by: Claudiu Beznea <claudiu.beznea@xxxxxxxxx>
[ryan.wanner@microchip: Add SAMA7D65 and SAM9X75 SoCs to the changes.
Change how the main_xtal and slcks are initialized so they match the
parent_data API]
Signed-off-by: Ryan Wanner <Ryan.Wanner@xxxxxxxxxxxxx>
---
drivers/clk/at91/at91rm9200.c | 2 +-
drivers/clk/at91/at91sam9260.c | 2 +-
drivers/clk/at91/at91sam9g45.c | 2 +-
drivers/clk/at91/at91sam9n12.c | 2 +-
drivers/clk/at91/at91sam9x5.c | 2 +-
drivers/clk/at91/clk-usb.c | 41 +++++++++++++++++++++
+------------
drivers/clk/at91/dt-compat.c | 6 ++---
drivers/clk/at91/pmc.h | 11 +++++----
drivers/clk/at91/sam9x60.c | 2 +-
drivers/clk/at91/sam9x7.c | 21 +++++++++--------
drivers/clk/at91/sama5d2.c | 2 +-
drivers/clk/at91/sama5d3.c | 2 +-
drivers/clk/at91/sama5d4.c | 2 +-
drivers/clk/at91/sama7d65.c | 24 +++++++++++---------
14 files changed, 72 insertions(+), 49 deletions(-)
[ ... ]
@@ -882,10 +885,10 @@ static void __init sam9x7_pmc_setup(struct
device_node *np)
sam9x7_pmc->chws[PMC_MCK] = hw;
- parent_names[0] = "plla_divpmcck";
- parent_names[1] = "upll_divpmcck";
- parent_names[2] = "main_osc";
- usbck_hw = sam9x60_clk_register_usb(regmap, "usbck",
parent_names, 3);
+ parent_data[0] = AT91_CLK_PD_HW(sam9x7_plls[PLL_ID_PLLA]
[PLL_COMPID_DIV0].hw);
+ parent_data[1] = AT91_CLK_PD_HW(sam9x7_plls[PLL_ID_UPLL]
[PLL_COMPID_DIV0].hw);
+ parent_data[2] = AT91_CLK_PD_HW(main_osc_hw);
+ usbck_hw = sam9x60_clk_register_usb(regmap, "usbck", NULL,
parent_data, 3);
sam9x60_clk_register_usb() could be converted to use parent_hws
member of
struct clk_init_data instead of parent_data.
So this would mean that I would pass in an array of the plls as
parent_hws, and use that to load the clk_init_data struct instead of
filling the array of parent_data as it is changed to in this patch set?
And this would be functionally the same since parent_data points to
clk_hw?>
It should be something like:
I see, I guess my question is why the usbclk system only? Is it just due
to how little parents there are for the usbclk? Or is it because this is
the only clock that only uses clk_hw for all of its parents?
Thank you,
Claudiu