Re: [PATCH 04/22] clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1}_DIV7 clocks

[Geert Uytterhoeven]

On Wed, 26 Nov 2025 at 15:08, Tommaso Merciai
<tommaso.merciai.xr@xxxxxxxxxxxxxx> wrote:
> Add the CLK_PLLDSI0_DIV7 and CLK_PLLDSI1_DIV7 fixed-factor clocks to
> the r9a09g047 SoC clock driver.
>
> These clocks are required to enable LVDS0 and LVDS1 output support.
>
> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@xxxxxxxxxxxxxx>

Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds