Re: [PATCH v2 13/13] ARM: dts: r9a06g032: Describe the QSPI controller

From: Geert Uytterhoeven

Date: Thu Jan 15 2026 - 08:01:05 EST


Hi Miquel,

On Thu, 15 Jan 2026 at 10:25, Miquel Raynal (Schneider Electric)
<miquel.raynal@xxxxxxxxxxx> wrote:
> Add a node describing the QSPI controller.
> There are 2 clocks feeding this controller:
> - one for the reference clock
> - one that feeds both the ahb and the apb interfaces
> As the binding expect either the ref clock, or all three (ref, ahb and
> apb) clocks, it makes sense to provide the same clock twice.
>
> Signed-off-by: Miquel Raynal (Schneider Electric) <miquel.raynal@xxxxxxxxxxx>

Thanks for your patch!

> --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi
> +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi
> @@ -66,6 +66,20 @@ soc {
> #size-cells = <1>;
> ranges;
>
> + qspi0: spi@40005000 {
> + compatible = "renesas,r9a06g032-qspi", "renesas,rzn1-qspi", "cdns,qspi-nor";
> + reg = <0x40005000 0x1000>, <0x10000000 0x10000000>;
> + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&sysctrl R9A06G032_CLK_QSPI0>, <&sysctrl R9A06G032_HCLK_QSPI0>,
> + <&sysctrl R9A06G032_HCLK_QSPI0>;
> + clock-names = "ref", "ahb", "apb";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cdns,fifo-width = <4>;

<4> is the default, right?

> + cdns,trigger-address = <0>;

Where in the RZ/N1 docs can I find if these two properties are correct?

> + status = "disabled";
> + };
> +
> rtc0: rtc@40006000 {
> compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc";
> reg = <0x40006000 0x1000>;

The rest LGTM, ignoring my comments on the bindings:
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds