Re: [PATCH v3 09/10] arm64: dts: qcom: kaanapali: Add support for MM clock controllers for Kaanapali

[Dmitry Baryshkov]

On Wed, Jan 14, 2026 at 10:49:11PM -0800, Jingyi Wang wrote:
> From: Taniya Das <taniya.das@xxxxxxxxxxxxxxxx>
> 
> Add the device nodes for the multimedia clock controllers(cambistmclkcc,

Somebody took away a whitespace from the previous line.

> camcc, dispcc, videocc, gpucc and gxclkctl).
> 
> Signed-off-by: Taniya Das <taniya.das@xxxxxxxxxxxxxxxx>
> Signed-off-by: Jingyi Wang <jingyi.wang@xxxxxxxxxxxxxxxx>
> ---
>  arch/arm64/boot/dts/qcom/kaanapali.dtsi | 102 ++++++++++++++++++++++++++++++++
>  1 file changed, 102 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> index 30705483ca20..8689715ae24f 100644
> --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> @@ -3,7 +3,13 @@
>   * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
>   */
>  
> +#include <dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h>
> +#include <dt-bindings/clock/qcom,kaanapali-camcc.h>
> +#include <dt-bindings/clock/qcom,kaanapali-dispcc.h>
>  #include <dt-bindings/clock/qcom,kaanapali-gcc.h>
> +#include <dt-bindings/clock/qcom,kaanapali-gpucc.h>
> +#include <dt-bindings/clock/qcom,kaanapali-gxclkctl.h>
> +#include <dt-bindings/clock/qcom,kaanapali-videocc.h>
>  #include <dt-bindings/clock/qcom,rpmh.h>
>  #include <dt-bindings/clock/qcom,sm8750-tcsr.h>
>  #include <dt-bindings/dma/qcom-gpi.h>
> @@ -1594,6 +1600,24 @@ aggre_noc: interconnect@16e0000 {
>  				 <&rpmhcc RPMH_IPA_CLK>;
>  		};
>  
> +		cambistmclkcc: clock-controller@1760000 {
> +			compatible = "qcom,kaanapali-cambistmclkcc";
> +			reg = <0x0 0x1760000 0x0 0x6000>;

0x01760000 (and similar issue with other reg properties).

> +
> +			clocks = <&gcc GCC_CAM_BIST_MCLK_AHB_CLK>,
> +				 <&bi_tcxo_div2>,
> +				 <&bi_tcxo_ao_div2>,
> +				 <&sleep_clk>;
> +
> +			power-domains = <&rpmhpd RPMHPD_MMCX>,
> +					<&rpmhpd RPMHPD_MX>;
> +			required-opps = <&rpmhpd_opp_low_svs>,
> +					<&rpmhpd_opp_low_svs>;
> +
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;

Is it a reset controller?

> +		};
> +
>  		mmss_noc: interconnect@1780000 {
>  			compatible = "qcom,kaanapali-mmss-noc";
>  			reg = <0x0 0x01780000 0x0 0x5b800>;

> +
> +		dispcc: clock-controller@9ba2000 {
> +			compatible = "qcom,kaanapali-dispcc";
> +			reg = <0x0 0x9ba2000 0x0 0x20000>;
> +			clocks = <&bi_tcxo_div2>,
> +				 <&bi_tcxo_ao_div2>,
> +				 <&gcc GCC_DISP_AHB_CLK>,
> +				 <&sleep_clk>,
> +				 <0>, <0>, <0>, <0>,
> +				 <0>, <0>, <0>, <0>,
> +				 <0>, <0>, <0>, <0>;

One zero per line. Or two, if you want to pair DP and DSI clock entries.

> +
> +			power-domains = <&rpmhpd RPMHPD_MMCX>;
> +			required-opps = <&rpmhpd_opp_low_svs>;
> +
> +			#clock-cells = <1>;
> +			#power-domain-cells = <1>;
> +			#reset-cells = <1>;
> +		};
> +
>  		pdc: interrupt-controller@b220000 {
>  			compatible = "qcom,kaanapali-pdc", "qcom,pdc";
>  			reg = <0x0 0x0b220000 0x0 0x10000>,
> 
> -- 
> 2.25.1
> 

-- 
With best wishes
Dmitry