Re: [PATCH v3 01/11] dt-bindings: riscv: add SpacemiT X100 CPU compatible

[Paul Walmsley]

On Thu, 8 Jan 2026, Guodong Xu wrote:

> Add compatible string for the SpacemiT X100 core. [1]
> 
> The X100 is a 64-bit RVA23-compliant RISC-V core from SpacemiT. X100
> supports the RISC-V vector and hypervisor extensions and all mandatory
> extersions as required by the RVA23U64 and RVA23S64 profiles, per the
> definition in 'RVA23 Profile, Version 1.0'. [2]
> 
> >From a microarchieture viewpoint, the X100 features a 4-issue
> out-of-order pipeline.
> 
> X100 is used in SpacemiT K3 SoC.
> 
> Link: https://www.spacemit.com/en/spacemit-x100-core/ [1]
> Link: https://docs.riscv.org/reference/profiles/rva23/_attachments/rva23-profile.pdf [2]
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxxxxxxxx>
> Reviewed-by: Yixun Lan <dlan@xxxxxxxxxx>
> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@xxxxxxxxxxxxx>
> Signed-off-by: Guodong Xu <guodong@xxxxxxxxxxxx>

I think Yixun Lan is going to pick this up, so 

Acked-by: Paul Walmsley <pjw@xxxxxxxxxx>


- Paul