Re: [PATCH v5 3/3] counter: Add STM based counter

From: Daniel Lezcano

Date: Wed Jan 14 2026 - 11:38:59 EST


On 1/13/26 19:01, Frank Li wrote:
On Tue, Jan 13, 2026 at 05:52:20PM +0100, Daniel Lezcano wrote:
The NXP S32G2 automotive platform integrates four Cortex-A53 cores and
three Cortex-M7 cores, along with a large number of timers and
counters. These hardware blocks can be used as clocksources or
clockevents, or as timestamp counters shared across the various
subsystems running alongside the Linux kernel, such as firmware
components. Their actual usage depends on the overall platform
software design.

In a Linux-based system, the kernel controls the counter, which is a
read-only shared resource for the other subsystems. One of its primary
purposes is to act as a common timestamp source for messages or
traces, allowing correlation of events occurring in different
operating system contexts.

These changes introduce a basic counter driver that can start, stop,
and reset the counter. It also handles overflow accounting and
configures the prescaler value.

Signed-off-by: Daniel Lezcano <daniel.lezcano@xxxxxxxxxx>
---

[ ... ]

+static int nxp_stm_cnt_count_read(struct counter_device *dev,
+ struct counter_count *count, u64 *val)
+{
+ struct nxp_stm_cnt *stm_cnt = counter_priv(dev);
+ u32 w1, w2, cnt;
+
+ do {
+ w1 = atomic_read(&stm_cnt->nr_wraps);
+ cnt = nxp_stm_cnt_get_counter(stm_cnt);
+ w2 = atomic_read(&stm_cnt->nr_wraps);
+ } while (w1 != w2);

Still have problem. Does hardware have overflow flags? This way is just
work for hardware overflow

No, there is no overflow flag. Just a comparator.

CPU1

w1 = 0
count = 0xffff,ffff
w2 = 0


when count wrap to 0, triger irq, but irq handle have latency at CPU0,
CPU0 have not chance to sevice irq. you can add printk at irq sevice to
create corner case.

So CPU1 get

w1= 0
count = 0
w2=0

so counter still suddently change to 0.

Ok, so I think I'll stick to the initial implementation and just give the counter number instead of trying to do fancy things.


[ ... ]

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