Re: [PATCH 3/3] iommu/vt-d: Rework hitless PASID entry replacement
From: Baolu Lu
Date: Wed Jan 14 2026 - 01:03:57 EST
On 1/13/26 23:05, Jason Gunthorpe wrote:
On Tue, Jan 13, 2026 at 11:00:48AM +0800, Lu Baolu wrote:
+static inline bool pasid_support_hitless_replace(struct pasid_entry *pte,
+ struct pasid_entry *new, int type)
+{
+ switch (type) {
+ case PASID_ENTRY_PGTT_FL_ONLY:
+ case PASID_ENTRY_PGTT_NESTED:
+ /* The first 128 bits remain the same. */
+ return READ_ONCE(pte->val[0]) == READ_ONCE(new->val[0]) &&
+ READ_ONCE(pte->val[1]) == READ_ONCE(new->val[1]);
pte->val128[0] == new->val128[0]
+ case PASID_ENTRY_PGTT_SL_ONLY:
+ case PASID_ENTRY_PGTT_PT:
+ /* The second 128 bits remain the same. */
+ return READ_ONCE(pte->val[2]) == READ_ONCE(new->val[2]) &&
+ READ_ONCE(pte->val[3]) == READ_ONCE(new->val[3]);
These READ_ONCE's are pointless, especially the ones on new.
With 5 words to worry about I really feel strongly this should just
use the ARM algorithm. It handles everything very elegantly, we can
lift it out of ARM and make it general.
Here, I did a quick refactoring into general code:
https://github.com/jgunthorpe/linux/commits/for-baolu/
You just need to provide a used function to compute which bits HW is
not ignoring and a sync function to push the invalidation command. It
will take care of all sequencing needs for all possible new/old
combinations.
It's always good to generate common library code to avoid boilerplate
code and different behaviors across multiple drivers. I'll try to
integrate this into the next version. Thanks for the help!
Then delete the replace/not replace split in the code too.
Jason
Thanks,
baolu