Re: [PATCH v2] pwm: tiehrpwm: Enable EHRPWM controller before setting configuration
From: Gokul Praveen
Date: Mon Jan 19 2026 - 01:48:59 EST
Hi Rafael.
On 19/01/26 08:25, Rafael V. Volkmer wrote:
Hello Uwe, Gokul,
Sorry for the late response, I was on vacation and away from my setup.
On Fri, 9 Jan 2026 23:53:22 +0100, Uwe Kleine-König wrote:
That makes me think the problem isn't understood well yet and needs more
research. @Rafael, does the problem reproduce for you with Gokul's
recipe? (Or did you try that already? I understood your reply as "I
didn't encounter the issue but also didn't test specifically for that.")
Right, my previous reply meant I hadn't explicitly targeted this issue yet.
I have now re-tested using Gokul's sysfs configuration sequence, but I still
cannot reproduce it on my setup.
As I cannot reproduce the issue, can you please check if adding
pm_runtime_get_sync(pwmchip_parent(chip));
to the probe function makes the problem disappear? Also please boot with
trace_event=pwm
on the command line and provide the content of
/sys/kernel/debug/tracing/trace after reproducing the problem.
Since I cannot reproduce the issue here, I can't validate whether adding
pm_runtime_get_sync() changes the behavior, and I don't have a failing
trace to share.
For reference, I ran the tests on an AM62P EVM using TI's default SDK
userspace, with a custom kernel on top, and U-Boot from the SDK. The
board was booted from SD card.
I used pwm1 instead of pwm0, since the PWM pin routed to the EVM 40-pin
header is ball B21 (SPI0_CLK / EHRPWM1_A). The signal was verified with a
logic analyzer at 24 MHz sampling rate.
This makes me suspect the behavior Gokul observed might depend on another
configuration interacting in parallel.
If possible, could Gokul try the same recipe on an AM62 EVM using TI's
default images and confirm whether the issue reproduces there? That is the
platform I am currently working with. This should either match the AM62P
results or help identify a relevant configuration difference.
Can you test the same on TI J784S4 EVM as I reproduced the issue on this board.
I believe dumping the registers and capturing the signals using logic analyzer is the best way to reproduce this issue.
The easiest way I tried to reproduce this issue is by enabling debug prints. I have attached the patch for the same(0001-Debug-prints-to-check-if-period-and-duty-cycle-is-re.patch). This patch basically reads the registers and prints its value.
So, after applying the attached patch and running the following commands, I got the following output.
Commands:
============
>>>>> cd /sys/class/pwm/pwmchip0
>>>>> /sys/class/pwm/pwmchip0# echo 1 > export
>>>>> /sys/class/pwm/pwmchip0# cd pwm1/
>>>>> /sys/class/pwm/pwmchip0/pwm1# echo 10000000 > period
>>>>> /sys/class/pwm/pwmchip0/pwm1# echo 3000000 > duty_cycle
>>>>> /sys/class/pwm/pwmchip0/pwm1# echo "normal" > polarity
>>>>> /sys/class/pwm/pwmchip0/pwm1# echo 1 > enable
========================================================
Output:
===========
Before put sync: Period:65103, Duty cycle:19531
EHRPWM enable function: Period:0, Duty cycle:0
===================================================
This indicates that the duty cycle and period is not reflected.
It would be really helpful, if you can try the same procedure on J784S4 EVM, Rafael. I have also attached a patch(0001-Enable-EHRPWM-1_B-using AC33-pin.patch) which includes the device tree changes for enabling EHRPWM1_B. The testpoint used for signal capture is TP126.
Additionally, it would be great if you can also share the output after applying the attached patch((0001-Debug-prints-to-check-if-period-and-duty-cycle-is-re.patch) on both AM62 EVM and J784S4 EVM.
The issue is that I do not have an AM62 EVM with me, actually. Apologies for that, Rafael.
Thanks in advance for your help, Rafael.
Best Regards
Gokul Praveen
Best regards,From 793171b857a7c37c838d882b2610b89d6ef90e1a Mon Sep 17 00:00:00 2001
Rafael V. Volkmer
From: Gokul Praveen <g-praveen@xxxxxx>
Date: Fri, 16 Jan 2026 14:31:02 +0530
Subject: [PATCH] Debug prints to check if period and duty cycle is reflected
or not
Signed-off-by: Gokul Praveen <g-praveen@xxxxxx>
---
drivers/pwm/pwm-tiehrpwm.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c
index 7a86cb090f76..3626375c5e4a 100644
--- a/drivers/pwm/pwm-tiehrpwm.c
+++ b/drivers/pwm/pwm-tiehrpwm.c
@@ -283,6 +283,7 @@ static int ehrpwm_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
ehrpwm_write(pc->mmio_base, TBPRD, period_cycles - 1);
+
/* Configure ehrpwm counter for up-count mode */
ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CTRMODE_MASK,
TBCTL_CTRMODE_UP);
@@ -290,7 +291,15 @@ static int ehrpwm_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
if (!(duty_cycles > period_cycles))
ehrpwm_write(pc->mmio_base, cmp_reg, duty_cycles);
+ u16 duty_cycle = ehrpwm_read(pc->mmio_base, CMPB);
+ u16 period = ehrpwm_read(pc->mmio_base, TBPRD);
+
+ printk("Before put sync: Period:%u, Duty cycle:%u\n",(unsigned int)period,(unsigned int)duty_cycle);
pm_runtime_put_sync(pwmchip_parent(chip));
+
+ //duty_cycle = ehrpwm_read(pc->mmio_base, CMPB);
+ //period = ehrpwm_read(pc->mmio_base, TBPRD);
+ //printk("After put sync: Period:%d, Duty cycle:%d\n",period,duty_cycle);
return 0;
}
@@ -304,6 +313,10 @@ static int ehrpwm_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
/* Leave clock enabled on enabling PWM */
pm_runtime_get_sync(pwmchip_parent(chip));
+ u16 duty_cycle = ehrpwm_read(pc->mmio_base, CMPB);
+ u16 period = ehrpwm_read(pc->mmio_base, TBPRD);
+ printk("EHRPWM enable function: Period:%u, Duty cycle:%u\n",(unsigned int)period,(unsigned int)duty_cycle);
+
/* Disabling Action Qualifier on PWM output */
if (pwm->hwpwm) {
aqcsfrc_val = AQCSFRC_CSFB_FRCDIS;
@@ -327,6 +340,7 @@ static int ehrpwm_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
return ret;
}
+
return 0;
}
--
2.34.1
From d4da610f7104f254e7dc5f9d7f6aa1b112fda287 Mon Sep 17 00:00:00 2001
From: Gokul Praveen <g-praveen@xxxxxx>
Date: Thu, 15 Jan 2026 14:52:59 +0530
Subject: [PATCH] Enable EHRPWM 1_B using AC33 pin Enable PWM EVENT TRACING
---
.../boot/dts/ti/k3-j784s4-j742s2-common.dtsi | 1 +
.../dts/ti/k3-j784s4-j742s2-evm-common.dtsi | 18 ++++++++++++++++--
arch/arm64/configs/defconfig | 7 ++++++-
3 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi
index 1dceff119a47..af4103f159e3 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-common.dtsi
@@ -103,6 +103,7 @@ cbass_main: bus@100000 {
<0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT0 */
<0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT0 */
<0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
+ <0x00 0x03010000 0x00 0x03010000 0x00 0x00000100>, /*EHRPWM1*/
/* MCUSS_WKUP Range */
<0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi
index e50735577737..4a63ddeaa372 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi
@@ -296,6 +296,13 @@ J784S4_IOPAD(0x0e8, PIN_INPUT, 8) /* (AR38) TIMER_IO0.MMC1_SDCD */
>;
};
+ main_ehrpwm1_pins_default: main-ehrpwm1-pins-default {
+ bootph-all;
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x074, PIN_OUTPUT, 9) /* (AC33) EHRPWM1_B.GPIO0_29 */
+ >;
+ };
+
vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
pinctrl-single,pins = <
J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */
@@ -661,6 +668,13 @@ &mcu_uart0 {
pinctrl-0 = <&mcu_uart0_pins_default>;
};
+&main_ehrpwm1 {
+ /* EHRPWM1*/
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_ehrpwm1_pins_default>;
+ status = "okay";
+};
+
&main_uart8 {
bootph-all;
status = "okay";
@@ -852,7 +866,7 @@ p15-hog {
/* P15 - CANUART_MUX1_SEL1 */
gpio-hog;
gpios = <15 GPIO_ACTIVE_HIGH>;
- output-high;
+ output-low;
line-name = "CANUART_MUX1_SEL1";
};
};
@@ -888,7 +902,7 @@ &main_sdhci0 {
&main_sdhci1 {
bootph-all;
/* SD card */
- status = "okay";
+ status = "disabled";
pinctrl-0 = <&main_mmc1_pins_default>;
pinctrl-names = "default";
disable-wp;
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 45288ec9eaf7..d08d9346e848 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1643,7 +1643,7 @@ CONFIG_PWM_STM32=m
CONFIG_PWM_SUN4I=m
CONFIG_PWM_TEGRA=m
CONFIG_PWM_TIECAP=m
-CONFIG_PWM_TIEHRPWM=m
+CONFIG_PWM_TIEHRPWM=y
CONFIG_PWM_VISCONTI=m
CONFIG_SL28CPLD_INTC=y
CONFIG_QCOM_PDC=y
@@ -1859,6 +1859,10 @@ CONFIG_DEBUG_FS=y
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_PREEMPT is not set
# CONFIG_FTRACE is not set
+CONFIG_FTRACE=y
+CONFIG_TRACING=y
+CONFIG_EVENT_TRACING=y
+CONFIG_TRACING_SUPPORT=y
CONFIG_CORESIGHT=m
CONFIG_CORESIGHT_LINK_AND_SINK_TMC=m
CONFIG_CORESIGHT_CATU=m
@@ -1868,3 +1872,4 @@ CONFIG_CORESIGHT_STM=m
CONFIG_CORESIGHT_CPU_DEBUG=m
CONFIG_CORESIGHT_CTI=m
CONFIG_MEMTEST=y
+
--
2.34.1