Re: [PATCH 07/11] perf/amd/ibs: Support IBS_{FETCH|OP}_CTL2[Dis] to eliminate RMW race

[Ravi Bangoria]

Hi Dapeng,

>>  static int x86_pmu_amd_ibs_starting_cpu(unsigned int cpu)
>>  {
>>  	setup_APIC_ibs();
>> +
>> +	if (ibs_caps & IBS_CAPS_DIS) {
>> +		/*
>> +		 * IBS enable sequence:
>> +		 *   CTL[En] = 1;
>> +		 *   CTL2[Dis] = 0;
>> +		 *
>> +		 * IBS disable sequence:
>> +		 *   CTL2[Dis] = 1;
>> +		 *
>> +		 * Set CTL2[Dis] when CPU comes up. This is needed to make
>> +		 * enable sequence effective.
>> +		 */
>> +		wrmsrq(MSR_AMD64_IBSFETCHCTL2, 1);
>> +		wrmsrq(MSR_AMD64_IBSOPCTL2, 1);
> 
> What does the BIT 0 of these 2 MSRs mean? Disable? Better define a macro
> instead of using the magic number "1". 

Right, those are disable bits. I'll replace those magic numbers with
IBS_FETCH_2_DIS and IBS_OP_2_DIS.

Thanks,
Ravi