Re: [PATCH] clk: rs9: Convert to clk_hw_onecell_data and of_clk_hw_onecell_get()

[Marek Vasut]

On 1/19/26 4:23 PM, Geert Uytterhoeven wrote:
> rs9_of_clk_get() does not validate the clock index in the passed
> DT clock specifier.  If DT specifies an incorrect and out-of-range
> index, this may access memory beyond the end of the fixed-size clk_dif[]
> array.
>
> Instead of fixing this by adding a range check to rs9_of_clk_get(),
> convert the driver to use the of_clk_hw_onecell_get() helper, which
> already contains such a check.  Embedding a clk_hw_onecell_data
> structure in the rs9_driver_data structure has the added benefit that
> the clock array always has the correct size, and thus can no longer
> become out of sync when adding support for new rs9 variants.
>
> Fixes: 892e0ddea1aa6f70 ("clk: rs9: Add Renesas 9-series PCIe clock generator driver")
> Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
> ---
> While this patch applies on top of "[PATCH v2] clk: rs9: Reserve 8
> struct clk_hw slots for for 9FGV0841", it can be applied or backported
> without, by ignoring the change from "clk_dif[4]" to "clk_dif[8]".

Since the 9FGV0841 is the biggest part in the 9FGV series, the one-liner 
fix I posted is better suited as a stable backport. This rework 
shouldn't have the Fixes tag, since it is only that, a rework.

With that fixed:

Reviewed-by: Marek Vasut <marek.vasut+renesas@xxxxxxxxxxx>