Re: [PATCH v7 3/4] i2c: tegra: Add logic to support different register offsets
From: Kartik Rajput
Date: Tue Jan 20 2026 - 00:26:13 EST
Hi Jon,
Thanks for reviewing the patch!
On 20/01/26 02:31, Jon Hunter wrote:
On 13/01/2026 16:59, Kartik Rajput wrote:
Tegra410 use different offsets for existing I2C registers, update
the logic to use appropriate offsets per SoC.
As the registers offsets are now also defined for dvc and vi, following
function are not required and they are removed:
- tegra_i2c_reg_addr(): No translation required.
- dvc_writel(): Replaced with i2c_writel() with DVC check.
This says dvc_writel is replace, but ...
Yes, the commit message needs to be updated.
- dvc_readl(): Replaced with i2c_readl().
Signed-off-by: Kartik Rajput <kkartik@xxxxxxxxxx>
---
Changes in v7:
* Fix Tegra256 reg offsets, change it to tegra264_i2c_regs as it
supports SW mutex.
Changes in v6:
* Do not remove dvc_writel().
This says it isn't and ...
/**
@@ -348,45 +466,26 @@ static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
writel_relaxed(val, i2c_dev->base + reg);
}
-static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned int reg)
-{
- return readl_relaxed(i2c_dev->base + reg);
-}
If we are removing dvc_readl() I am not sure why we have not removed dvc_writel().
static void tegra_i2c_dma_complete(void *args)
@@ -621,12 +720,12 @@ static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
{
u32 val;
- val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
+ val = i2c_readl(i2c_dev, DVC_CTRL_REG3);
val |= DVC_CTRL_REG3_SW_PROG;
val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
- val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
+ val = i2c_readl(i2c_dev, DVC_CTRL_REG1);
val |= DVC_CTRL_REG1_INTR_EN;
dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
}
We could just call writel_relaxed() directly if we can't use i2c_writel().
Jon
This makes sense, we are not doing anything special in the dvc_writel(), it can be
replaced with writel_relaxed() directly.
Thanks,
Kartik