RE: [PATCH v2 2/5] clk: versaclock3: Use clk_parent_data arrays for clk_mux

[Fabrizio Castro]

> From: Ovidiu Panait <ovidiu.panait.rb@xxxxxxxxxxx>
> Sent: 20 January 2026 15:06
> To: geert+renesas@xxxxxxxxx; magnus.damm <magnus.damm@xxxxxxxxx>; robh@xxxxxxxxxx; krzk+dt@xxxxxxxxxx;
> conor+dt@xxxxxxxxxx; mturquette@xxxxxxxxxxxx; sboyd@xxxxxxxxxx; Biju Das <biju.das.jz@xxxxxxxxxxxxxx>;
> Fabrizio Castro <fabrizio.castro.jz@xxxxxxxxxxx>
> Cc: linux-renesas-soc@xxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; linux-
> clk@xxxxxxxxxxxxxxx
> Subject: [PATCH v2 2/5] clk: versaclock3: Use clk_parent_data arrays for clk_mux
> 
> Replace the inline parent_hws initializers with static clk_parent_data
> arrays for the clk muxes. This provides more flexibility in how
> parents are described and will simplify extending the parent lists in
> the next commit.
> 
> Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@xxxxxxxxxxx>

Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@xxxxxxxxxxx>

> ---
> v2 changes: None.
> 
>  drivers/clk/clk-versaclock3.c | 48 ++++++++++++++++++++---------------
>  1 file changed, 28 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/clk/clk-versaclock3.c b/drivers/clk/clk-versaclock3.c
> index f387cdb12f48..ebd9d75d7f55 100644
> --- a/drivers/clk/clk-versaclock3.c
> +++ b/drivers/clk/clk-versaclock3.c
> @@ -900,6 +900,29 @@ static struct vc3_hw_data clk_div[] = {
>  	}
>  };
> 
> +static const struct clk_parent_data clk_mux_parent_data[][2] = {
> +	[VC3_SE1_MUX] = {
> +		{ .hw = &clk_div[VC3_DIV5].hw },
> +		{ .hw = &clk_div[VC3_DIV4].hw }
> +	},
> +	[VC3_SE2_MUX] = {
> +		{ .hw = &clk_div[VC3_DIV5].hw },
> +		{ .hw = &clk_div[VC3_DIV4].hw }
> +	},
> +	[VC3_SE3_MUX] = {
> +		{ .hw = &clk_div[VC3_DIV2].hw },
> +		{ .hw = &clk_div[VC3_DIV4].hw }
> +	},
> +	[VC3_DIFF1_MUX] = {
> +		{ .hw = &clk_div[VC3_DIV1].hw },
> +		{ .hw = &clk_div[VC3_DIV3].hw }
> +	},
> +	[VC3_DIFF2_MUX] = {
> +		{ .hw = &clk_div[VC3_DIV1].hw },
> +		{ .hw = &clk_div[VC3_DIV3].hw }
> +	},
> +};
> +
>  static struct vc3_hw_data clk_mux[] = {
>  	[VC3_SE1_MUX] = {
>  		.data = &(struct vc3_clk_data) {
> @@ -909,10 +932,7 @@ static struct vc3_hw_data clk_mux[] = {
>  		.hw.init = &(struct clk_init_data) {
>  			.name = "se1_mux",
>  			.ops = &vc3_clk_mux_ops,
> -			.parent_hws = (const struct clk_hw *[]) {
> -				&clk_div[VC3_DIV5].hw,
> -				&clk_div[VC3_DIV4].hw
> -			},
> +			.parent_data = clk_mux_parent_data[VC3_SE1_MUX],
>  			.num_parents = 2,
>  			.flags = CLK_SET_RATE_PARENT
>  		}
> @@ -924,10 +944,7 @@ static struct vc3_hw_data clk_mux[] = {
>  		.hw.init = &(struct clk_init_data) {
>  			.name = "se2_mux",
>  			.ops = &vc3_clk_mux_ops,
> -			.parent_hws = (const struct clk_hw *[]) {
> -				&clk_div[VC3_DIV5].hw,
> -				&clk_div[VC3_DIV4].hw
> -			},
> +			.parent_data = clk_mux_parent_data[VC3_SE2_MUX],
>  			.num_parents = 2,
>  			.flags = CLK_SET_RATE_PARENT
>  		}
> @@ -940,10 +957,7 @@ static struct vc3_hw_data clk_mux[] = {
>  		.hw.init = &(struct clk_init_data) {
>  			.name = "se3_mux",
>  			.ops = &vc3_clk_mux_ops,
> -			.parent_hws = (const struct clk_hw *[]) {
> -				&clk_div[VC3_DIV2].hw,
> -				&clk_div[VC3_DIV4].hw
> -			},
> +			.parent_data = clk_mux_parent_data[VC3_SE3_MUX],
>  			.num_parents = 2,
>  			.flags = CLK_SET_RATE_PARENT
>  		}
> @@ -956,10 +970,7 @@ static struct vc3_hw_data clk_mux[] = {
>  		.hw.init = &(struct clk_init_data) {
>  			.name = "diff1_mux",
>  			.ops = &vc3_clk_mux_ops,
> -			.parent_hws = (const struct clk_hw *[]) {
> -				&clk_div[VC3_DIV1].hw,
> -				&clk_div[VC3_DIV3].hw
> -			},
> +			.parent_data = clk_mux_parent_data[VC3_DIFF1_MUX],
>  			.num_parents = 2,
>  			.flags = CLK_SET_RATE_PARENT
>  		}
> @@ -972,10 +983,7 @@ static struct vc3_hw_data clk_mux[] = {
>  		.hw.init = &(struct clk_init_data) {
>  			.name = "diff2_mux",
>  			.ops = &vc3_clk_mux_ops,
> -			.parent_hws = (const struct clk_hw *[]) {
> -				&clk_div[VC3_DIV1].hw,
> -				&clk_div[VC3_DIV3].hw
> -			},
> +			.parent_data = clk_mux_parent_data[VC3_DIFF2_MUX],
>  			.num_parents = 2,
>  			.flags = CLK_SET_RATE_PARENT
>  		}
> --
> 2.51.0