Re: [PATCH v2 1/4 RESEND] clk: tegra20: reparent dsi clock to pll_d_out0

[Thierry Reding]

On Thu, Dec 04, 2025 at 08:17:00AM +0200, Svyatoslav Ryhel wrote:
> Reparent DSI clock to PLLD_OUT0 instead of directly descend from PLLD.
> 
> Signed-off-by: Svyatoslav Ryhel <clamor95@xxxxxxxxx>
> Acked-by: Stephen Boyd <sboyd@xxxxxxxxxx>
> ---
>  drivers/clk/tegra/clk-tegra20.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)

Applied, thanks.

Thierry

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