Re: [PATCH v4 3/5] dt-bindings: pinctrl: document polarfire soc mssio pin controller

[Rob Herring (Arm)]

On Tue, 20 Jan 2026 18:15:41 +0000, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
> 
> On Polarfire SoC, the Bank 2 and Bank 4 IOs connected to the
> Multiprocessor Subsystem (MSS) are controlled by IOMUX_CRs 1 through 6,
> which determine what function in routed to them, and
> MSSIO_BANK#_IO_CFG_CRs, which determine the configuration of each pin.
> 
> Document it, including several custom configuration options that stem
> from MSS Configurator options (the MSS Configurator is part of the FPGA
> tooling for this device). "ibufmd" unfortunately is not a 1:1 mapping
> with an MSS Configurator option, unlike clamp-diode or lockdown, and I
> do not know the effect of any bits in the field. I have no been able to
> find an explanation for these bits in documentation.
> 
> Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
> ---
>  .../pinctrl/microchip,mpfs-pinctrl-mssio.yaml | 109 ++++++++++++++++++
>  .../microchip,mpfs-mss-top-sysreg.yaml        |   4 +
>  2 files changed, 113 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-mssio.yaml
> 

Reviewed-by: Rob Herring (Arm) <robh@xxxxxxxxxx>