[PATCH v1 1/5] dt-bindings: memory: Document Tegra114 Memory Controller

From: Svyatoslav Ryhel

Date: Mon Jan 26 2026 - 14:08:13 EST


Add Tegra114 support into existing Tegra124 MC schema with the most
notable difference in the amount of EMEM timings.

Signed-off-by: Svyatoslav Ryhel <clamor95@xxxxxxxxx>
Reviewed-by: Rob Herring (Arm) <robh@xxxxxxxxxx>
---
.../nvidia,tegra124-mc.yaml | 31 +++++--------------
1 file changed, 8 insertions(+), 23 deletions(-)

diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml
index 7b18b4d11e0a..f8747cebb680 100644
--- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml
@@ -19,7 +19,9 @@ description: |

properties:
compatible:
- const: nvidia,tegra124-mc
+ enum:
+ - nvidia,tegra114-mc
+ - nvidia,tegra124-mc

reg:
maxItems: 1
@@ -64,29 +66,12 @@ patternProperties:

nvidia,emem-configuration:
$ref: /schemas/types.yaml#/definitions/uint32-array
- description: |
+ description:
Values to be written to the EMEM register block. See section
- "15.6.1 MC Registers" in the TRM.
- items:
- - description: MC_EMEM_ARB_CFG
- - description: MC_EMEM_ARB_OUTSTANDING_REQ
- - description: MC_EMEM_ARB_TIMING_RCD
- - description: MC_EMEM_ARB_TIMING_RP
- - description: MC_EMEM_ARB_TIMING_RC
- - description: MC_EMEM_ARB_TIMING_RAS
- - description: MC_EMEM_ARB_TIMING_FAW
- - description: MC_EMEM_ARB_TIMING_RRD
- - description: MC_EMEM_ARB_TIMING_RAP2PRE
- - description: MC_EMEM_ARB_TIMING_WAP2PRE
- - description: MC_EMEM_ARB_TIMING_R2R
- - description: MC_EMEM_ARB_TIMING_W2W
- - description: MC_EMEM_ARB_TIMING_R2W
- - description: MC_EMEM_ARB_TIMING_W2R
- - description: MC_EMEM_ARB_DA_TURNS
- - description: MC_EMEM_ARB_DA_COVERS
- - description: MC_EMEM_ARB_MISC0
- - description: MC_EMEM_ARB_MISC1
- - description: MC_EMEM_ARB_RING1_THROTTLE
+ "20.11.1 MC Registers" in the Tegea114 TRM or
+ "15.6.1 MC Registers" in the Tegra124 TRM.
+ minItems: 18
+ maxItems: 19

required:
- clock-frequency
--
2.51.0