RE: [Intel-wired-lan] [PATCH iwl-next v6] ice: add support for unmanaged DPLL on E830 NIC

[Mekala, SunithaX D]

> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces@xxxxxxxxxx> On Behalf Of Arkadiusz Kubalewski
> Sent: Tuesday, January 20, 2026 5:05 AM
> To: intel-wired-lan@xxxxxxxxxxxxxxxx
> Cc: pmenzel@xxxxxxxxxxxxx; linux-doc@xxxxxxxxxxxxxxx; netdev@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; Kubalewski, Arkadiusz <arkadiusz.kubalewski@xxxxxxxxx>; Loktionov, > Aleksandr <aleksandr.loktionov@xxxxxxxxx>; Nguyen, Anthony L <anthony.l.nguyen@xxxxxxxxx>; Fodor, Zoltan <zoltan.fodor@xxxxxxxxx>; horms@xxxxxxxxxx; Kitszel, Przemyslaw > <przemyslaw.kitszel@xxxxxxxxx>; Grinberg, Vitaly <vgrinber@xxxxxxxxxx>
> Subject: [Intel-wired-lan] [PATCH iwl-next v6] ice: add support for unmanaged DPLL on E830 NIC
>
> Hardware variants of E830 may support an unmanaged DPLL where the
> configuration is hardcoded within the hardware and firmware, meaning
> users cannot modify settings. However, users are able to check the DPLL
> lock status and obtain configuration information through the Linux DPLL
> and devlink health subsystem.
>
> Availability of 'loss of lock' health status code determines if such
> support is available, if true, register single DPLL device with 1 input
> and 1 output and provide hardcoded/read only properties of a pin and
> DPLL device. User is only allowed to check DPLL device status and receive
> notifications on DPLL lock status change.
>
> When present, the DPLL device locks to an external signal provided
> through the PCIe/OCP pin. The expected input signal is 1PPS
> (1 Pulse Per Second) embedded on a 10MHz reference clock.
> The DPLL produces output:
> - for MAC (Media Access Control) & PHY (Physical Layer) clocks,
> - 1PPS for synchronization of onboard PHC (Precision Hardware Clock) timer.
>
> Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@xxxxxxxxx>
> Reviewed-by: Paul Menzel <pmenzel@xxxxxxxxxxxxx>
> Signed-off-by: Grzegorz Nitka <grzegorz.nitka@xxxxxxxxx>
> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@xxxxxxxxx>
> ---
> v6:
> - change dpll type EEC -> PPS, this dpll serves both functionalisites but PPS
>  is superset of EEC type
> - use DPLL_MODE_MANUAL instead of AUTOMATIC, which is correct for the input
>   pins that doesn't have capability to set the priority
> v5:
> - rebased (baseline does not include dependent e825C patches now)
> - added health status notification (thru devlink and DPLL subsystem)
> v4:
> - add correct strcuture for reading supported health status codes and
>  use it to parse the outcome of 0xFF21 AQ command.
> ---
>  .../device_drivers/ethernet/intel/ice.rst     |  83 +++++
>  .../net/ethernet/intel/ice/devlink/health.c   |   4 +
>  .../net/ethernet/intel/ice/ice_adminq_cmd.h   |  12 +
>  drivers/net/ethernet/intel/ice/ice_common.c   | 135 ++++++++
>  drivers/net/ethernet/intel/ice/ice_common.h   |   8 +
>  drivers/net/ethernet/intel/ice/ice_dpll.c     | 310 ++++++++++++++++--
>  drivers/net/ethernet/intel/ice/ice_dpll.h     |  11 +
>  drivers/net/ethernet/intel/ice/ice_main.c     |  14 +-
>  drivers/net/ethernet/intel/ice/ice_ptp_hw.c   |  46 +++
>  drivers/net/ethernet/intel/ice/ice_ptp_hw.h   |   1 +
>  10 files changed, 602 insertions(+), 22 deletions(-)

Tested-by: Sunitha Mekala <sunithax.d.mekala@xxxxxxxxx> (A Contingent worker at Intel)