Re: [PATCH v3 2/2] PCI/ACPI: Confine program_hpx_type2 to the AER bits

[Haakon Bugge]

>>> Thanks for the word-smithing and improved accuracy!
>>> 
>>> +	/* Log if _HPX attempts to modify PCIe Link Control register */
>>> 	if (pcie_cap_has_lnkctl(dev)) {
>>> -
>>> -		/*
>>> -		 * If the Root Port supports Read Completion Boundary of
>>> -		 * 128, set RCB to 128.  Otherwise, clear it.
>>> -		 */
>>> -		hpx->pci_exp_lnkctl_and |= PCI_EXP_LNKCTL_RCB;
>>> -		hpx->pci_exp_lnkctl_or &= ~PCI_EXP_LNKCTL_RCB;
>>> -		if (pcie_root_rcb_set(dev))
>>> -			hpx->pci_exp_lnkctl_or |= PCI_EXP_LNKCTL_RCB;
>>> -
>>> -		pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
>>> -			~hpx->pci_exp_lnkctl_and, hpx->pci_exp_lnkctl_or);
>>> 
> This was what confused me a lot, the bit-wise NOT above. That must be wrong, as pcie_capability_clear_and_set_word() inverts the "clear" argument.

Have to correct myself here. ACPI states:

When configuring a given register, OSPM uses the following algorithm:
1. Read the register’s current value, which contains the register’s default value.
2. Perform a bit-wise AND operation with the “AND mask” from the table below.
[]

Because pcie_capability_clear_and_set_word() inverts the "clear" argument, the above bitwise NOT is of course correct. Two bitwise NOTs is a no-op and we follow the ACPI outlined algorithm.


Sorry for the noise, Håkon