Re: [PATCH net-next 2/2] net: phy: dp83867: Always program R/SGMII enable bits

[Russell King (Oracle)]

On Thu, Jan 29, 2026 at 12:12:05PM -0500, Sean Anderson wrote:
> If the board designers have neglected to populate the appropriate
> resistors on the strapping pins then the phy may default to the wrong
> interface mode. Enable/disable the RGMII/SGMII enable bits as necessary
> to select the correct interface.
> 
> The dp83867 strapping pins have four levels and typically configure two
> features at once. LED_0 controls both port mirroring and whether SGMII
> is enabled. If it is pulled to VDDIO, both port mirroring and SGMII
> will be enabled. For variants of the dp83867 that do not support SGMII,
> this will prevent data from being transferred. As we now explicitly set
> the SGMII and RGMII enable bits, we do not need to detect whether SGMII
> has been inadvertently enabled.
> 
> Signed-off-by: Sean Anderson <sean.anderson@xxxxxxxxx>

Something to consider:

You have separate enable bits for SGMII and RGMII. The code you're
submitting sets the SGMII enable before clearing the RGMII enable.
Is it permitted to have both set?

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