Re: [PATCH v3 2/7] media: iris: introduce SM8350 and SC8280XP support

[Dikshita Agarwal]

On 1/26/2026 4:25 PM, Dmitry Baryshkov wrote:
> On Mon, Jan 26, 2026 at 10:50:56AM +0100, Konrad Dybcio wrote:
>> On 1/25/26 4:32 PM, Dmitry Baryshkov wrote:
>>> SM8350 and SC8280XP have an updated version of the Iris2 core also
>>> present on the SM8250 and SC7280 platforms. Add necessary platform data
>>> to utilize the core on those two platforms.
>>>
>>> The iris_platform_gen1.c is now compiled unconditionally, even if Venus
>>> driver is enabled, but SM8250 and SC7280 are still disabled in
>>> iris_dt_match.
>>>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxxxxxxxx>
>>> ---
>>
>> [...]
>>
>>> +static void iris_set_sm8350_preset_registers(struct iris_core *core)
>>> +{
>>> +	u32 val;
>>> +
>>> +	val = readl(core->reg_base + 0xb0088);
>>> +	val &= ~0x11;
>>> +	writel(val, core->reg_base + 0xb0088);
>>
>> Can we "open-source" what this write does?
> 
> I'd leave this question to Vikash. Hopefully he can comment if I can
> open these bits or not.

This register controls the clock halt states for several IRIS sub‑cores.
A bit value of 1 halts the clock, and 0 enables it.
During power‑on, we clear bits 0 and 4 to unhalt/enable the corresponding
core clocks.

Thanks,
Dikshita
>