Re: [PATCH 4/4] sched/fair: Proportional newidle balance
From: Mohamed Abuelfotoh, Hazem
Date: Fri Jan 30 2026 - 11:13:40 EST
On 29/01/2026 09:24, Peter Zijlstra wrote:
CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you can confirm the sender and know the content is safe.We don't enable Intel-CAT to partition L3 cache between VMs.
On Thu, Jan 29, 2026 at 10:19:37AM +0100, Peter Zijlstra wrote:
On Wed, Jan 28, 2026 at 03:48:13PM +0000, Mohamed Abuelfotoh, Hazem wrote:
Below are the hardware specs for both c7i.4xlarge & c7a.4xlarge.
c7i.4xlarge
CPU Model: Intel(R) Xeon(R) Platinum 8488C
Number of CPUs: 16
Memory: 32 GB
Number of sockets: 1
But the 8488C is a 56 core part, with 112 threads. So you're handing out
8 core partitions of that thing, for 7 such instances on one machine?
(Also, calling anything 16 core with 32GB 'large' is laughable, that's
laptop territory.)
Also, are you employing Intel-CAT on these partitions to separate the
L3s?
(Not immediately relevant I suppose, but I was curious)