Re: [PATCH] dt-bindings: dma: snps,dw-axi-dmac: add dma-coherent property

[Dinh Nguyen]

On 1/31/26 14:27, Conor Dooley wrote:
> On Sat, Jan 31, 2026 at 11:28:56AM -0600, Dinh Nguyen wrote:
> > From: Khairul Anuar Romli <khairul.anuar.romli@xxxxxxxxxx>
> >
> > The Synopsys DesignWare AXI DMA Controller on Agilex5, the controller
> > operates on a cache-coherent AXI interface, where DMA transactions are
> > automatically kept coherent with the CPU caches. In previous generations
> > SoC (Stratix10 and Agilex) the interconnect was non-coherent, hence there
> > is no need for dma-coherent property to be presence. In Agilex 5, the
> > architecture has changed. It  introduced a coherent interconnect that
> > supports cache-coherent DMA.
> >
> > Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@xxxxxxxxxx>
> > Reviewed-by: Rob Herring (Arm) <robh@xxxxxxxxxx>
>
> Why does this v1 have an ack?

I respun this patch based on the dmaengine tree so that the dma engine 
maintainer can take it. I had originally applied it to my tree, but 
avoid potential merge conflicts, I'm going to submit it through dma. 
This patch is the same as this[1].

Sorry for any confusion.

Dinh
[1] 
https://lore.kernel.org/linux-devicetree/176488420978.2206697.11201292177123636920.robh@xxxxxxxxxx/