Re: [PATCH v6 3/4] arm64: dts: qcom: Introduce Glymur base dtsi

[Pankaj Patil]

On 1/31/2026 3:30 AM, Abel Vesa wrote:
> On 26-01-30 23:44:43, Abel Vesa wrote:
>> On 26-01-22 20:54:00, Pankaj Patil wrote:
>>> Introduce the base device tree support for Glymur – Qualcomm's
>>> next-generation compute SoC. The new glymur.dtsi describes the core SoC
>>> components, including:
>>>
>>> - CPUs and CPU topology
>>> - Interrupt controller and TLMM
>>> - GCC,DISPCC and RPMHCC clock controllers
>>> - Reserved memory and interconnects
>>> - APPS and PCIe SMMU and firmware SCM
>>> - Watchdog, RPMHPD, APPS RSC and SRAM
>>> - PSCI and PMU nodes
>>> - QUPv3 serial engines
>>> - CPU power domains and idle states, plus SCMI/ SRAM pieces for CPU DVFS
>>> - PDP0 mailbox, IPCC and AOSS
>>> - Display clock controller
>>> - SPMI PMIC arbiter with SPMI0/1/2 buses
>>> - SMP2P nodes
>>> - TSENS and thermal zones (8 instances, 92 sensors)
>>>
>>> Add dtsi files for PMH0101, PMK8850, PMCX0102, SMB2370, PMH0104,
>>> PMH0110, PMIC's along with temp-alarm and GPIO nodes needed on Glymur
>>>
>>> Enabled PCIe controllers and associated PHY to support boot to
>>> shell with nvme storage,
>>> List of PCIe instances enabled:
>>>
>>> - PCIe3b
>>> - PCIe4
>>> - PCIe5
>>> - PCIe6
>>>
>>> Co-developed-by: Jyothi Kumar Seerapu <jyothi.seerapu@xxxxxxxxxxxxxxxx>
>>> Signed-off-by: Jyothi Kumar Seerapu <jyothi.seerapu@xxxxxxxxxxxxxxxx>
>>> Co-developed-by: Maulik Shah <maulik.shah@xxxxxxxxxxxxxxxx>
>>> Signed-off-by: Maulik Shah <maulik.shah@xxxxxxxxxxxxxxxx>
>>> Co-developed-by: Sibi Sankar <sibi.sankar@xxxxxxxxxxxxxxxx>
>>> Signed-off-by: Sibi Sankar <sibi.sankar@xxxxxxxxxxxxxxxx>
>>> Co-developed-by: Taniya Das <taniya.das@xxxxxxxxxxxxxxxx>
>>> Signed-off-by: Taniya Das <taniya.das@xxxxxxxxxxxxxxxx>
>>> Co-developed-by: Kamal Wadhwa <kamal.wadhwa@xxxxxxxxxxxxxxxx>
>>> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@xxxxxxxxxxxxxxxx>
>>> Co-developed-by: Qiang Yu <qiang.yu@xxxxxxxxxxxxxxxx>
>>> Signed-off-by: Qiang Yu <qiang.yu@xxxxxxxxxxxxxxxx>
>>> Co-developed-by: Abel Vesa <abel.vesa@xxxxxxxxxx>
>>> Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxx>
>>> Co-developed-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@xxxxxxxxxxxxxxxx>
>>> Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@xxxxxxxxxxxxxxxx>
>>> Co-developed-by: Jishnu Prakash <jishnu.prakash@xxxxxxxxxxxxxxxx>
>>> Signed-off-by: Jishnu Prakash <jishnu.prakash@xxxxxxxxxxxxxxxx>
>>> Signed-off-by: Pankaj Patil <pankaj.patil@xxxxxxxxxxxxxxxx>
>>> ---
>>>  arch/arm64/boot/dts/qcom/glymur.dtsi         | 5913 ++++++++++++++++++++++++++
>>>  arch/arm64/boot/dts/qcom/pmcx0102.dtsi       |  187 +
>>>  arch/arm64/boot/dts/qcom/pmh0101.dtsi        |   68 +
>>>  arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi |  144 +
>>>  arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi |  144 +
>>>  arch/arm64/boot/dts/qcom/pmk8850.dtsi        |   70 +
>>>  arch/arm64/boot/dts/qcom/smb2370.dtsi        |   45 +
>>>  7 files changed, 6571 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
>>> new file mode 100644
>>> index 000000000000..16a3c3ecf97a
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
>>
>> [...]
>>
>>> +
>>> +	soc: soc@0 {
>>> +		compatible = "simple-bus";
>>> +		#address-cells = <2>;
>>> +		#size-cells = <2>;
>>> +		ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
>>> +		dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
>>> +
>>> +		gcc: clock-controller@100000 {
>>> +			compatible = "qcom,glymur-gcc";
>>> +			reg = <0x0 0x00100000 0x0 0x1f9000>;
>>> +			clocks = <&rpmhcc RPMH_CXO_CLK>,
>>> +				 <&rpmhcc RPMH_CXO_CLK_A>,
>>> +				 <&sleep_clk>,
>>> +				 <0>,
>>> +				 <0>,
>>> +				 <0>,
>>> +				 <0>,
>>> +				 <0>,
>>> +				 <0>,
>>> +				 <0>,
>>> +				 <0>,
>>> +				 <0>,
>>> +				 <0>,
>>> +				 <0>,
>>> +				 <0>,
>>> +				 <0>,
>>> +				 <0>,
>>> +				 <0>,
>>> +				 <0>,
>>> +				 <0>,
>>> +				 <&pcie3b_phy>,
>>> +				 <&pcie4_phy>,
>>> +				 <&pcie5_phy>,
>>> +				 <&pcie6_phy>,
>>
>> I'm afraid these do not match the array from the driver.
>> I think there is one more <0> before the pcie3b.
> 
> Actually, one less.
> 
>>
>> Please double check.

1 clock was removed in v4 to fix the no of clocks, 44 was incorrect
I will update it to match the array from the driver

>>
>> Thanks,
>> Abel