Re: [PATCH 1/3] dt-bindings: interconnect: qcom,qcs615-rpmh: add clocks property to enable QoS

[Konrad Dybcio]

On 2/2/26 8:05 AM, Odelu Kukatla wrote:
> Aggre1-noc interconnect node on QCS615 has QoS registers located
> inside a block whose interface is clock-gated. For that node,
> driver must enable the corresponding clock(s) before accessing
> the registers. Add the 'clocks' property so the driver can obtain
> and enable the required clock(s).
> 
> Only interconnects that have clock‑gated QoS register interface
> use this property; it is not applicable to all interconnect nodes.
> 
> Signed-off-by: Odelu Kukatla <odelu.kukatla@xxxxxxxxxxxxxxxx>
> ---
>  .../interconnect/qcom,qcs615-rpmh.yaml        | 44 +++++++++++++++++++
>  1 file changed, 44 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml
> index e06404828824..096a9064cc01 100644
> --- a/Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml
> +++ b/Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml
> @@ -34,6 +34,10 @@ properties:
>    reg:
>      maxItems: 1
>  
> +  clocks:
> +    minItems: 3
> +    maxItems: 3
> +
>  required:
>    - compatible
>  
> @@ -53,6 +57,36 @@ allOf:
>        required:
>          - reg
>  
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - qcom,qcs615-aggre1-noc
> +    then:
> +      properties:
> +        clocks:
> +          items:
> +            - description: aggre UFS PHY AXI clock
> +            - description: aggre USB2 SEC AXI clock
> +            - description: aggre USB3 PRIM AXI clock

Should we also include the IPA clock here?

Konrad