Re: [PATCH net-next] net: stmmac: dwmac-loongson: Set clk_csr_i to 100-150MHz

[Huacai Chen]

Hi, Andrew,

On Tue, Feb 3, 2026 at 5:42 AM Andrew Lunn <andrew@xxxxxxx> wrote:
>
> On Sun, Feb 01, 2026 at 10:37:00AM +0800, Huacai Chen wrote:
> > Current clk_csr_i setting of Loongson STMMAC (including LS7A1000/2000
> > and LS2K1000/2000/3000) are copy & paste from other drivers. In fact,
> > Loongson STMMAC use 125MHz clocks and need 62 freq division to within
> > 2.5MHz, meeting most PHY MDC requirement. So fix by setting clk_csr_i
> > to 100-150MHz.
> >
> > Cc: stable@xxxxxxxxxxxxxxx
> > Signed-off-by: Hongliang Wang <wanghongliang@xxxxxxxxxxx>
> > Signed-off-by: Huacai Chen <chenhuacai@xxxxxxxxxxx>
>
> Fixes tag?
OK, will add it.

>
> Does the error mean that MDC is ticking at 9.7Mhz? That is pretty fast
> for PHYs. But i assume it must work for some boards.
Yes, some PHYs work while others don't.

Huacai
>
> Separate to this fix, you might be interested in:
>
>   clock-frequency:
>     description:
>       Desired MDIO bus clock frequency in Hz. Values greater than IEEE 802.3
>       defined 2.5MHz should only be used when all devices on the bus support
>       the given clock speed.
>
> So you could allow faster MDC values using this property.
>
>     Andrew
>
> ---
> pw-bot: cr