Re: [PATCH v2 1/4] clk: renesas: rzg2l: Drop a check in rzg3s_cpg_pll_clk_recalc_rate()

[Claudiu Beznea]

On 1/30/26 13:58, Biju wrote:
> From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
>
> Drop the unwanted check in rzg3s_cpg_pll_clk_recalc_rate() as the function
> is SoC specific.
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>

Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>

> ---
> v1->v2:
>   * No change
> ---
>   drivers/clk/renesas/rzg2l-cpg.c | 3 ---
>   1 file changed, 3 deletions(-)
>
> diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
> index 16771a0101bd..ee92d07c6ff7 100644
> --- a/drivers/clk/renesas/rzg2l-cpg.c
> +++ b/drivers/clk/renesas/rzg2l-cpg.c
> @@ -1113,9 +1113,6 @@ static unsigned long rzg3s_cpg_pll_clk_recalc_rate(struct clk_hw *hw,
>   	u32 nir, nfr, mr, pr, val, setting;
>   	u64 rate;
>   
> -	if (pll_clk->type != CLK_TYPE_G3S_PLL)
> -		return parent_rate;
> -
>   	setting = GET_REG_SAMPLL_SETTING(pll_clk->conf);
>   	if (setting) {
>   		val = readl(priv->base + setting);