Re: [PATCH v3 1/7] dt-bindings: clock: qcom,sm8250-videocc: account for the MX domain

[Dmitry Baryshkov]

On Thu, Feb 05, 2026 at 12:31:54PM +0100, Krzysztof Kozlowski wrote:
> On Wed, Feb 04, 2026 at 02:59:49AM +0200, Dmitry Baryshkov wrote:
> > To configure the video PLLs and enable the video GDSCs on SM8250,
> > platform, the MX rail must be ON along with MMCX. Split the bindings
> > file in order to provide separate file utilizing MMCX and MX power
> > domains.
> 
> ...
> 
> > +
> > +description: |
> > +  Qualcomm video clock control module provides the clocks, resets and power
> > +  domains on Qualcomm SoCs.
> > +
> > +  See also::
> 
> Only one ':', please. It was a mistake to introduce ::

Ack.

> 
> > +  clock-names:
> > +    items:
> > +      - const: iface
> > +      - const: bi_tcxo
> > +      - const: bi_tcxo_ao
> > +
> > +  power-domains:
> > +    items:
> > +      - description:
> > +          A phandle and PM domain specifier for the MMCX power domain.
> > +      - description:
> > +          A phandle and PM domain specifier for the MX power domain.
> 
> This is an ABI break, so please say in the commit what was not working
> or why this ABI break is really justified. Currently you just give a
> hint that it is needed for PLL configuration, but honestly - why would
> we care to configure PLL if everything was working correct before?

I must admit, I c&p'ed the commit message from [1] which was ack'ed by
Rob and accepted into the kernel. What is the difference?

[1] https://lore.kernel.org/all/20250530-videocc-pll-multi-pd-voting-v5-1-02303b3a582d@xxxxxxxxxxx/

-- 
With best wishes
Dmitry