RE: [PATCH v3 0/9] Add RZ/G3L IRQC support

[Biju Das]

Hi Thomas Gleixner,

Thanks for the feedback.

> -----Original Message-----
> From: Thomas Gleixner <tglx@xxxxxxxxxx>
> Sent: 06 February 2026 11:38
> Subject: Re: [PATCH v3 0/9] Add RZ/G3L IRQC support
> 
> On Fri, Feb 06 2026 at 11:16, Biju wrote:
> > From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> >
> > The IRQC block on RZ/G3L SoC is almost identical to one found on the
> > RZ/G3S SoC with the difference like it support more External IRQs, GPT
> > Error Interrupts and also has additional registers for GPT/MTU IRQ
> > selection, shared IRQ selection between external IRQ and TINT.
> >
> > It has 16 external interrupts of which 8 interrupts are shared with
> > TINT[24:31] and are mutually exclusive. The external IRQ/TINT IRQ
> > selection is based on a register in the ICU block.
> 
> Can you please give people the time to actually look at your patches before you repost the full series
> every other day?

Sorry for that. Will take care next time.

Thanks,
Biju