Re: [PATCH v3 19/19] drm/amd/display: Add HDMI VRR desktop mode
From: Harry Wentland
Date: Fri Feb 06 2026 - 13:58:43 EST
On 2026-02-03 13:56, Tomasz Pakuła wrote:
> [Why]
> Many TVs and other HDMI sinks suffer from blanking and possibly other
> glitches when VRR is toggled. With FreeSync present on such sinks, they
> behave like the signal is always variable, even in fixed refresh rate
> situations.
>
> [How]
> Keep HDMI VRR toggled if it's supported and not explicitly disabled.
> Additionnally, add module parameter which allows users to configure HDMI
> VRR triggering to only happen when the signal is truly asking for
> variable state. This is useful if end user has a TV that automatically
> toggles ALLM/Game mode when VRR is active and such user doesn't want
> gaming mode in normal desktop usage.
>
Can't this already be done by the compositor by simply setting the
VRR_ENABLED property on a crtc?
I don't like doing behavior behind the backs of compositors that
they might not be expecting.
Harry
> Signed-off-by: Tomasz Pakuła <tomasz.pakula.oficjalny@xxxxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 13 +++++++++++++
> .../amd/display/modules/info_packet/info_packet.c | 9 +++++++--
> 3 files changed, 21 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 312aa32064d5..d49cd55e0f35 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -269,6 +269,7 @@ extern int amdgpu_rebar;
> extern int amdgpu_wbrf;
> extern int amdgpu_user_queue;
> extern uint amdgpu_allm_mode;
> +extern bool amdgpu_hdmi_vrr_desktop_mode;
>
> extern uint amdgpu_hdmi_hpd_debounce_delay_ms;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 4b038c8bbf9f..f53c2ffeffa2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -249,6 +249,7 @@ int amdgpu_rebar = -1; /* auto */
> int amdgpu_user_queue = -1;
> uint amdgpu_hdmi_hpd_debounce_delay_ms;
> uint amdgpu_allm_mode = 1;
> +bool amdgpu_hdmi_vrr_desktop_mode = true;
>
> DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0,
> "DRM_UT_CORE",
> @@ -1146,6 +1147,18 @@ module_param_named(hdmi_hpd_debounce_delay_ms, amdgpu_hdmi_hpd_debounce_delay_ms
> MODULE_PARM_DESC(allm_mode, "Changes ALLM trigger mode (0 = disable, 1 = enable (default), 2 = force enable)");
> module_param_named(allm_mode, amdgpu_allm_mode, uint, 0644);
>
> +/**
> + * DOC: hdmi_vrr_on_dekstop (bool)
> + * Enables FreeSync behavior mimicking by keeping HDMI VRR signalling active in
> + * fixed refresh rate conditions like normal desktop work/web browsing.
> + * Possible values:
> + *
> + * - false = HDMI VRR is only enabled if refresh rate is truly variable
> + * - true = Mimics FreeSync behavior and keeps HDMI VRR always active
> + */
> +MODULE_PARM_DESC(hdmi_vrr_desktop_mode, "Changes HDMI VRR desktop mode (false = disable, true = enable (default))");
> +module_param_named(hdmi_vrr_desktop_mode, amdgpu_hdmi_vrr_desktop_mode, bool, 0644);
> +
> /* These devices are not supported by amdgpu.
> * They are supported by the mach64, r128, radeon drivers
> */
> diff --git a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
> index 5fd9e8aadc98..b41e2240e1ae 100644
> --- a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
> +++ b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
> @@ -654,8 +654,13 @@ static void build_vtem_infopacket_data(const struct dc_stream_state *stream,
> bool vrr_active = false;
> bool rb = false;
>
> - vrr_active = vrr->state == VRR_STATE_ACTIVE_VARIABLE ||
> - vrr->state == VRR_STATE_ACTIVE_FIXED;
> + if (amdgpu_hdmi_vrr_desktop_mode) {
> + vrr_active = vrr->state != VRR_STATE_UNSUPPORTED &&
> + vrr->state != VRR_STATE_DISABLED;
> + } else {
> + vrr_active = vrr->state == VRR_STATE_ACTIVE_VARIABLE ||
> + vrr->state == VRR_STATE_ACTIVE_FIXED;
> + }
>
> infopacket->sb[VTEM_MD0] = VTEM_M_CONST << VTEM_M_CONST_BIT;
> infopacket->sb[VTEM_MD0] |= VTEM_FVA_FACTOR << VTEM_FVA_BIT;