[PATCH 0/3] arm64: qcom: sm8550: add DDR, LLCC & L3 CPU bandwidth scaling

[Aaron Kling via B4 Relay]

Add the OSM L3 controller node then add the necessary interconnect
properties with the appropriate OPP table for each CPU cluster to
allow the DDR, LLCC & L3 CPU bandwidth to scale along the CPU
cluster operating point.

Signed-off-by: Aaron Kling <webgeek1234@xxxxxxxxx>
---
Aaron Kling (3):
      arm64: dts: qcom: sm8550: add OSM L3 node
      arm64: dts: qcom: sm8550: add cpu interconnect nodes
      arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths

 arch/arm64/boot/dts/qcom/sm8550.dtsi | 367 +++++++++++++++++++++++++++++++++++
 1 file changed, 367 insertions(+)
---
base-commit: 9845cf73f7db6094c0d8419d6adb848028f4a921
change-id: 20260207-sm8550-ddr-bw-scaling-b1524827f207

Best regards,
-- 
Aaron Kling <webgeek1234@xxxxxxxxx>