Re: [PATCH 2/3] arm64: dts: qcom: sm8550: add cpu interconnect nodes

[Krzysztof Kozlowski]

On 08/02/2026 02:28, Aaron Kling via B4 Relay wrote:
> From: Aaron Kling <webgeek1234@xxxxxxxxx>
> 
> Add the interconnect entry for each cpu, with 3 different paths:
> - CPU to Last Level Cache Controller (LLCC)
> - Last Level Cache Controller (LLCC) to DDR
> - L3 Cache from CPU to DDR interface
> 
> Signed-off-by: Aaron Kling <webgeek1234@xxxxxxxxx>
> ---
>  arch/arm64/boot/dts/qcom/sm8550.dtsi | 49 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 49 insertions(+)
> 

This patch should be squashed. You add interconnect and use it,
otherwise it is pretty pointless or even negatively impacting (syncing
without interconnect paths).

Best regards,
Krzysztof