RE: [PATCH] iommu/vt-d: fix intel iommu iotlb sync hardlockup & retry

[Tian, Kevin]

> From: guanghuifeng@xxxxxxxxxxxxxxxxx <guanghuifeng@xxxxxxxxxxxxxxxxx>
> Sent: Thursday, February 5, 2026 6:28 PM
> 
> There are a few points that need clarification:
> The descriptors between head and tail are requests that have not been
> fetched and executed.
> 
> 
> Regarding the requests before the head:
> Method 1: Does the IOMMU update the head address register immediately
> after fetching the descriptor?
> Method 2: Or does the IOMMU update the head register only after fetching
> and executing the request?
> 
> The current Intel IOMMU VT-d specification does not describe this
> behavior in detail.
> Does the IOMMU currently use Method 1?
> 

It's clearly documented in the VT-d spec, 6.5.2 Queued Invalidation
Interface:

"
Invalidation Queue Head Register: This register points to the invalidation
descriptor in the IQ that hardware will process next. The Invalidation
Queue Head register is incremented by hardware after fetching a valid
descriptor from the IQ.
"

"
Hardware implementations may fetch one or more descriptors together.
However, hardware must increment the Invalidation Queue Head Register
only after verifying the fetched descriptor to be valid.
"

the wait descriptor is for synchronizing with hardware completion.