Re: [PATCH 1/3] phy: qcom: edp: Correct and clean up eDP/DP combo PHY configuration values

[Yongxing Mou]

On 2/7/2026 6:22 PM, Dmitry Baryshkov wrote:
> On Thu, Feb 05, 2026 at 05:20:53PM +0800, Yongxing Mou wrote:
> > According to the current HPG settings, most eDP/DP combo PHYs can reuse the
> > same configuration values.
> > DP mode：
> > 	-sa8775p/sc7280/sc8280xp/x1e80100
> > 	-glymur
> > eDP mode(low vdiff):
> > 	-glymur/sa8775p/sc8280xp/x1e80100
> > 	-sc7280
> > The current driver still keeps multiple versions of these tables and
> > doesn't fully support every combo PHY mode. This patch removes the
>
> See Documentation/process/submitting-patches.rst, "This patch".
Sure. got it thanks, will remove "This patch".
> > redundant configs and keeps only the sets we actually use, matching the
> > platforms listed above.
>
> Should it be combined with the 3rd patch? There you sort out all the
> tables, it makes more sense to review all programming together.
Hi, if this would help with your review work, I’m very happy to do it.
My original intention was to do some cleanup in this patch—correct the 
table values so that more platforms can reuse the same table.
From Konard’s comments, it seems that the HPG table may not be the most 
appropriate one either.
Maybe shoud first determine what the correct table values should be.
> > Signed-off-by: Yongxing Mou <yongxing.mou@xxxxxxxxxxxxxxxx>
> > ---
> >   drivers/phy/qualcomm/phy-qcom-edp.c | 41 +++++++++----------------------------
> >   1 file changed, 10 insertions(+), 31 deletions(-)
> >
> > diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c
> > index 13feab99feec..10cbb7d9a8a0 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-edp.c
> > +++ b/drivers/phy/qualcomm/phy-qcom-edp.c
> > @@ -116,17 +116,17 @@ struct qcom_edp {
> >   };
> >   
> >   static const u8 dp_swing_hbr_rbr[4][4] = {
> > -	{ 0x08, 0x0f, 0x16, 0x1f },
> > +	{ 0x07, 0x0f, 0x16, 0x1f },
> >   	{ 0x11, 0x1e, 0x1f, 0xff },
> >   	{ 0x16, 0x1f, 0xff, 0xff },
> >   	{ 0x1f, 0xff, 0xff, 0xff }
> >   };
> >   
> >   static const u8 dp_pre_emp_hbr_rbr[4][4] = {
> > -	{ 0x00, 0x0d, 0x14, 0x1a },
> > +	{ 0x00, 0x0e, 0x15, 0x1a },
> >   	{ 0x00, 0x0e, 0x15, 0xff },
> >   	{ 0x00, 0x0e, 0xff, 0xff },
> > -	{ 0x03, 0xff, 0xff, 0xff }
> > +	{ 0x04, 0xff, 0xff, 0xff }
> >   };
> >   
> >   static const u8 dp_swing_hbr2_hbr3[4][4] = {
> > @@ -158,7 +158,7 @@ static const u8 edp_swing_hbr_rbr[4][4] = {
> >   };
> >   
> >   static const u8 edp_pre_emp_hbr_rbr[4][4] = {
> > -	{ 0x05, 0x12, 0x17, 0x1d },
> > +	{ 0x05, 0x11, 0x17, 0x1d },
> >   	{ 0x05, 0x11, 0x18, 0xff },
> >   	{ 0x06, 0x11, 0xff, 0xff },
> >   	{ 0x00, 0xff, 0xff, 0xff }
> > @@ -172,10 +172,10 @@ static const u8 edp_swing_hbr2_hbr3[4][4] = {
> >   };
> >   
> >   static const u8 edp_pre_emp_hbr2_hbr3[4][4] = {
> > -	{ 0x08, 0x11, 0x17, 0x1b },
> > -	{ 0x00, 0x0c, 0x13, 0xff },
> > -	{ 0x05, 0x10, 0xff, 0xff },
> > -	{ 0x00, 0xff, 0xff, 0xff }
> > +	{ 0x0c, 0x15, 0x19, 0x1e },
> > +	{ 0x0b, 0x15, 0x19, 0xff },
> > +	{ 0x0e, 0x14, 0xff, 0xff },
> > +	{ 0x0d, 0xff, 0xff, 0xff }
> >   };
> >   
> >   static const struct qcom_edp_swing_pre_emph_cfg edp_phy_swing_pre_emph_cfg = {
> > @@ -193,27 +193,6 @@ static const u8 edp_phy_vco_div_cfg_v4[4] = {
> >   	0x01, 0x01, 0x02, 0x00,
> >   };
> >   
> > -static const u8 edp_pre_emp_hbr_rbr_v5[4][4] = {
> > -	{ 0x05, 0x11, 0x17, 0x1d },
> > -	{ 0x05, 0x11, 0x18, 0xff },
> > -	{ 0x06, 0x11, 0xff, 0xff },
> > -	{ 0x00, 0xff, 0xff, 0xff }
> > -};
> > -
> > -static const u8 edp_pre_emp_hbr2_hbr3_v5[4][4] = {
> > -	{ 0x0c, 0x15, 0x19, 0x1e },
> > -	{ 0x0b, 0x15, 0x19, 0xff },
> > -	{ 0x0e, 0x14, 0xff, 0xff },
> > -	{ 0x0d, 0xff, 0xff, 0xff }
> > -};
> > -
> > -static const struct qcom_edp_swing_pre_emph_cfg edp_phy_swing_pre_emph_cfg_v5 = {
> > -	.swing_hbr_rbr = &edp_swing_hbr_rbr,
> > -	.swing_hbr3_hbr2 = &edp_swing_hbr2_hbr3,
> > -	.pre_emphasis_hbr_rbr = &edp_pre_emp_hbr_rbr_v5,
> > -	.pre_emphasis_hbr3_hbr2 = &edp_pre_emp_hbr2_hbr3_v5,
> > -};
> > -
> >   static const u8 edp_phy_aux_cfg_v5[DP_AUX_CFG_SIZE] = {
> >   	0x00, 0x13, 0xa4, 0x00, 0x0a, 0x26, 0x0a, 0x03, 0x37, 0x03, 0x02, 0x02, 0x00,
> >   };
> > @@ -564,7 +543,7 @@ static const struct qcom_edp_phy_cfg sa8775p_dp_phy_cfg = {
> >   	.is_edp = false,
> >   	.aux_cfg = edp_phy_aux_cfg_v5,
> >   	.vco_div_cfg = edp_phy_vco_div_cfg_v4,
> > -	.swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg_v5,
> > +	.swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg,
> >   	.ver_ops = &qcom_edp_phy_ops_v4,
> >   };
> >   
> > @@ -944,7 +923,7 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v8 = {
> >   static struct qcom_edp_phy_cfg glymur_phy_cfg = {
> >   	.aux_cfg = edp_phy_aux_cfg_v8,
> >   	.vco_div_cfg = edp_phy_vco_div_cfg_v8,
> > -	.swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg_v5,
> > +	.swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg,
> >   	.ver_ops = &qcom_edp_phy_ops_v8,
> >   };
> >   
> >
> > --
> > 2.43.0