Re: [PATCH] perf/x86/intel/uncore: Add per-scheduler IMC CAS count events

[Mi, Dapeng]

On 2/10/2026 8:52 AM, Zide Chen wrote:
> IMC on SPR and EMR does not support sub-channels.  In contrast, CPUs
> that use gnr_uncores[] (e.g. Granite Rapids and Sierra Forest)
> implement two command schedulers (SCH0/SCH1) per memory channel,
> providing logically independent command and data paths.
>
> Do not reuse the spr_uncore_imc[] configuration for these CPUs.
> Instead, introduce a dedicated gnr_uncore_imc[] with per-scheduler
> events, so userspace can monitor SCH0 and SCH1 independently.
>
> On these CPUs, replace cas_count_{read,write} with
> cas_count_{read,write}_sch{0,1}.  This may break existing userspace
> that relies on cas_count_{read,write}, prompting it to switch to the
> per-scheduler events, as the legacy event reports only partial
> traffic (SCH0).
>
> Reported-by: Reinette Chatre <reinette.chatre@xxxxxxxxx>
> Fixes: 632c4bf6d007 ("perf/x86/intel/uncore: Support Granite Rapids")
> Fixes: cb4a6ccf3583 ("perf/x86/intel/uncore: Support Sierra Forest and Grand Ridge")
> Cc: stable@xxxxxxxxxxxxxxx
> Signed-off-by: Zide Chen <zide.chen@xxxxxxxxx>
> ---
>  arch/x86/events/intel/uncore_snbep.c | 28 +++++++++++++++++++++++++++-
>  1 file changed, 27 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
> index e513056f4562..b78a1782fc39 100644
> --- a/arch/x86/events/intel/uncore_snbep.c
> +++ b/arch/x86/events/intel/uncore_snbep.c
> @@ -6640,6 +6640,32 @@ static struct intel_uncore_type gnr_uncore_ubox = {
>  	.attr_update		= uncore_alias_groups,
>  };
>  
> +static struct uncore_event_desc gnr_uncore_imc_events[] = {
> +	INTEL_UNCORE_EVENT_DESC(clockticks,      "event=0x01,umask=0x00"),
> +	INTEL_UNCORE_EVENT_DESC(cas_count_read_sch0,  "event=0x05,umask=0xcf"),
> +	INTEL_UNCORE_EVENT_DESC(cas_count_read_sch0.scale, "6.103515625e-5"),
> +	INTEL_UNCORE_EVENT_DESC(cas_count_read_sch0.unit, "MiB"),
> +	INTEL_UNCORE_EVENT_DESC(cas_count_read_sch1,  "event=0x06,umask=0xcf"),
> +	INTEL_UNCORE_EVENT_DESC(cas_count_read_sch1.scale, "6.103515625e-5"),
> +	INTEL_UNCORE_EVENT_DESC(cas_count_read_sch1.unit, "MiB"),
> +	INTEL_UNCORE_EVENT_DESC(cas_count_write_sch0, "event=0x05,umask=0xf0"),
> +	INTEL_UNCORE_EVENT_DESC(cas_count_write_sch0.scale, "6.103515625e-5"),
> +	INTEL_UNCORE_EVENT_DESC(cas_count_write_sch0.unit, "MiB"),
> +	INTEL_UNCORE_EVENT_DESC(cas_count_write_sch1, "event=0x06,umask=0xf0"),
> +	INTEL_UNCORE_EVENT_DESC(cas_count_write_sch1.scale, "6.103515625e-5"),
> +	INTEL_UNCORE_EVENT_DESC(cas_count_write_sch1.unit, "MiB"),
> +	{ /* end: all zeroes */ },
> +};
> +
> +static struct intel_uncore_type gnr_uncore_imc = {
> +	SPR_UNCORE_MMIO_COMMON_FORMAT(),
> +	.name			= "imc",
> +	.fixed_ctr_bits		= 48,
> +	.fixed_ctr		= SNR_IMC_MMIO_PMON_FIXED_CTR,
> +	.fixed_ctl		= SNR_IMC_MMIO_PMON_FIXED_CTL,
> +	.event_descs		= gnr_uncore_imc_events,
> +};
> +
>  static struct intel_uncore_type gnr_uncore_pciex8 = {
>  	SPR_UNCORE_PCI_COMMON_FORMAT(),
>  	.name			= "pciex8",
> @@ -6687,7 +6713,7 @@ static struct intel_uncore_type *gnr_uncores[UNCORE_GNR_NUM_UNCORE_TYPES] = {
>  	NULL,
>  	&spr_uncore_pcu,
>  	&gnr_uncore_ubox,
> -	&spr_uncore_imc,
> +	&gnr_uncore_imc,
>  	NULL,
>  	&gnr_uncore_upi,
>  	NULL,

Reviewed-by: Dapeng Mi <dapeng1.mi@xxxxxxxxxxxxxxx>