Re: [PATCH RESEND 5/5] KVM: x86: selftests: Fix write MSR_TSC_AUX reserved bits test failure on Hygon

[Sean Christopherson]

On Wed, Feb 11, 2026, Zhiquan Li wrote:
> 
> On 2/11/26 04:02, Sean Christopherson wrote:
> > Gah, I think I tested -rdpid and -rdtscp in a VM on Intel, but not AMD.  I think
> > the fix is just this:
> > 
> > diff --git a/tools/testing/selftests/kvm/x86/msrs_test.c b/tools/testing/
> > selftests/kvm/x86/msrs_test.c
> > index 40d918aedce6..ebd900e713c1 100644
> > --- a/tools/testing/selftests/kvm/x86/msrs_test.c
> > +++ b/tools/testing/selftests/kvm/x86/msrs_test.c
> > @@ -175,7 +175,7 @@ void guest_test_reserved_val(const struct kvm_msr *msr)
> >          * If the CPU will truncate the written value (e.g. SYSENTER on AMD),
> >          * expect success and a truncated value, not #GP.
> >          */
> > - if (!this_cpu_has(msr->feature) ||
> > + if ((!this_cpu_has(msr->feature) && !this_cpu_has(msr->feature2)) ||
> >             msr->rsvd_val == fixup_rdmsr_val(msr->index, msr->rsvd_val)) {
> >                 u8 vec = wrmsr_safe(msr->index, msr->rsvd_val);
> 
> Perfect!  You found the root cause and fixed it.
> I’ve verified the fix on Hygon platform, I will test it on Intel and AMD
> platforms as well to make sure there is no regression.
> I’m going to include the you fix in the V2 series.  Since my modifications are
> totally miss the point, I will remove my SoB and only add my “Reported-by:” tag,
> I suppose the SoB position would be wait for you, Sean :-)

Nice!  Here's a full patch for v2.

--
From: Sean Christopherson <seanjc@xxxxxxxxxx>
Date: Wed, 11 Feb 2026 08:18:47 -0800
Subject: [PATCH] KVM: selftests: Fix reserved value WRMSR testcase for
 multi-feature MSRs

When determining whether or not a WRMSR with reserved bits will #GP or
succeed due to the WRMSR not existing per the guest virtual CPU model,
expect failure if and only if _all_ features associated with the MSR are
unsupported.  Checking only the primary feature results in false failures
when running on AMD and Hygon CPUs with only one of RDPID or RDTSCP, as
AMD/Hygon CPUs ignore MSR_TSC_AUX[63:32], i.e. don't treat the bits as
reserved, and so #GP only if the MSR is unsupported.

Fixes: 9c38ddb3df94 ("KVM: selftests: Add an MSR test to exercise guest/host and read/write")
Reported-by: Zhiquan Li <zhiquan_li@xxxxxxx>
Closes: https://lore.kernel.org/all/20260209041305.64906-6-zhiquan_li@xxxxxxx
Cc: stable@xxxxxxxxxxxxxxx
Signed-off-by: Sean Christopherson <seanjc@xxxxxxxxxx>
---
 tools/testing/selftests/kvm/x86/msrs_test.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/testing/selftests/kvm/x86/msrs_test.c b/tools/testing/selftests/kvm/x86/msrs_test.c
index 40d918aedce6..ebd900e713c1 100644
--- a/tools/testing/selftests/kvm/x86/msrs_test.c
+++ b/tools/testing/selftests/kvm/x86/msrs_test.c
@@ -175,7 +175,7 @@ void guest_test_reserved_val(const struct kvm_msr *msr)
 	 * If the CPU will truncate the written value (e.g. SYSENTER on AMD),
 	 * expect success and a truncated value, not #GP.
 	 */
-	if (!this_cpu_has(msr->feature) ||
+	if ((!this_cpu_has(msr->feature) && !this_cpu_has(msr->feature2)) ||
 	    msr->rsvd_val == fixup_rdmsr_val(msr->index, msr->rsvd_val)) {
 		u8 vec = wrmsr_safe(msr->index, msr->rsvd_val);
 

base-commit: e944fe2c09f405a2e2d147145c9b470084bc4c9a
--