[PATCH] clk: qcom: rpmh: Fix LNBBCLK3 divider for X1E80100

[Taniya Das]

The LNBBCLK3 clock used by the UFS controller runs at 38.4 MHz.
Update the divider value to generate the correct output frequency.

Fixes: 874bc7be1e08 ("clk: qcom: rpmh: Add support for X1E80100 rpmh clocks")
Signed-off-by: Taniya Das <taniya.das@xxxxxxxxxxxxxxxx>
---
 drivers/clk/qcom/clk-rpmh.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
index 547729b1a8ee01cf28c11ee8c4bd2f36d7536e6d..6e88f0a8d9b4c014928b095882b7150cabda6895 100644
--- a/drivers/clk/qcom/clk-rpmh.c
+++ b/drivers/clk/qcom/clk-rpmh.c
@@ -378,6 +378,7 @@ DEFINE_CLK_RPMH_VRM(clk2, _a1, "clka2", 1);
 DEFINE_CLK_RPMH_VRM(clk3, _a1, "clka3", 1);
 DEFINE_CLK_RPMH_VRM(clk4, _a1, "clka4", 1);
 DEFINE_CLK_RPMH_VRM(clk5, _a1, "clka5", 1);
+DEFINE_CLK_RPMH_VRM(clk8, _a1, "clka8", 1);
 
 DEFINE_CLK_RPMH_VRM(clk3, _a2, "clka3", 2);
 DEFINE_CLK_RPMH_VRM(clk4, _a2, "clka4", 2);
@@ -840,8 +841,8 @@ static struct clk_hw *x1e80100_rpmh_clocks[] = {
 	[RPMH_LN_BB_CLK1_A]	= &clk_rpmh_clk6_a2_ao.hw,
 	[RPMH_LN_BB_CLK2]	= &clk_rpmh_clk7_a2.hw,
 	[RPMH_LN_BB_CLK2_A]	= &clk_rpmh_clk7_a2_ao.hw,
-	[RPMH_LN_BB_CLK3]	= &clk_rpmh_clk8_a2.hw,
-	[RPMH_LN_BB_CLK3_A]	= &clk_rpmh_clk8_a2_ao.hw,
+	[RPMH_LN_BB_CLK3]	= &clk_rpmh_clk8_a1.hw,
+	[RPMH_LN_BB_CLK3_A]	= &clk_rpmh_clk8_a1_ao.hw,
 	[RPMH_RF_CLK3]		= &clk_rpmh_clk3_a2.hw,
 	[RPMH_RF_CLK3_A]	= &clk_rpmh_clk3_a2_ao.hw,
 	[RPMH_RF_CLK4]		= &clk_rpmh_clk4_a2.hw,

---
base-commit: 9152bc8cebcb14dc16b03ec81f2377ee8ce12268
change-id: 20260211-hamoa_ufs_clk8-9a7970ff90cb

Best regards,
-- 
Taniya Das <taniya.das@xxxxxxxxxxxxxxxx>