Re: [PATCH v1 5/5] ARM: tegra: configure Tegra114 power domains

[Svyatoslav Ryhel]

пт, 13 лют. 2026 р. о 05:44 Mikko Perttunen <mperttunen@xxxxxxxxxx> пише:
>
> On Tuesday, January 27, 2026 4:15 AM Svyatoslav Ryhel wrote:
> > Add power domains found in Tegra114 and configure operating-points-v2 for
> > supported devices accordingly.
> >
> > Signed-off-by: Svyatoslav Ryhel <clamor95@xxxxxxxxx>
> > ---
> >  .../dts/nvidia/tegra114-peripherals-opp.dtsi  | 1275 +++++++++++++++++
> >  arch/arm/boot/dts/nvidia/tegra114.dtsi        |  126 ++
> >  2 files changed, 1401 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi b/arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi
> > index b40a1c24abab..5e66c1dc8fb7 100644
> > --- a/arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi
> > +++ b/arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi
> > @@ -1,6 +1,76 @@
> >  // SPDX-License-Identifier: GPL-2.0
> >
...
> >
>
> I compared these core rail opps to what the roth (SHIELD Portable, T40T) kernel defines.
>
> The HW 0x1 (speedo 0) opps match process_id=0/speedo_id=0 perfectly except for msenc/vde/tsec where the curve ends at 408MHz at 1120mV. The roth kernel also specifies a process_id=1/speedo_id=0 with almost the same tables as process_id=1/speedo_id=1. process_id=0/speedo_id=1 doesn't exist.
>
> For HW 0x2 (speedo 1), when compared to process_id=1, the opps in the device tree are in some cases slightly conservative compared to what the roth kernel sets.
>
> So I think all of that should work (except maybe the msenc/vde/tsec curve extensions?), but it might be that there is some further potential on T40T. Hopefully these values are actually just a difference between T40X and T40T.
>
> In any case,
>

I might not have used the most recent T40S source. HW 0x1 table in
that source looks like this

_clk_name, _speedo_id, _process_id, _freqs
                                900,    950,   1000,   1050,    1100,
  1120,    1170,    1200,    1250,    1390
"msenc",   0,  0, 144000, 182000, 240000, 312000,  384000,  432000,
480000,  480000,  480000,  480000
"se",      0,  0, 144000, 182000, 240000, 312000,  384000,  432000,
480000,  480000,  480000,  480000
"tsec",    0,  0, 144000, 182000, 240000, 312000,  384000,  432000,
480000,  480000,  480000,  480000
"vde",     0,  0, 144000, 182000, 240000, 312000,  384000,  432000,
480000,  480000,  480000,  480000

I might adjust table for T40X and T40T since my source does not have
speedo 1 / process 0 (T40T) and has speedo 0 / process 1 (N/A) which
is odd. While creating these tables I assumed that speedo 0 / process
1 mapped to T40T and since T40T and T40X are linked, table from T40X
perspective looks conservative.

> Reviewed-by: Mikko Perttunen <mperttunen@xxxxxxxxxx>
>
>