Re: [PATCH] arm64: dts: qcom: qrb2210-arduino-imola: describe DSI / DP bridge

[Dmitry Baryshkov]

On Thu, Feb 12, 2026 at 10:40:41AM +0100, Konrad Dybcio wrote:
> On 2/11/26 10:28 AM, Dmitry Baryshkov wrote:
> > Aruino Uno-Q uses Analogix ANX7625 DSI-to-DP bridge to convert DSI
> > signals to the connected USB-C DisplayPort dongles. Decribe the chip,
> > USB-C connector and routing of USB and display signals.
> > 
> > Co-developed-by: Martino Facchin <m.facchin@xxxxxxxxxx>
> > Signed-off-by: Martino Facchin <m.facchin@xxxxxxxxxx>
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxxxxxxxx>
> > ---
> 
> [...]
> 
> >  #include <dt-bindings/leds/common.h>
> > +#include <dt-bindings/usb/pd.h>
> >  #include "agatti.dtsi"
> >  #include "pm4125.dtsi"
> >  
> > @@ -109,6 +110,16 @@ multi-led {
> >  		leds = <&ledr>, <&ledg>, <&ledb>;
> >  	};
> >  
> > +	vreg_anx_30: regulator-anx-30 {
> > +		/* ANX7625 VDD3 */
> 
> This comment is only mildly useful given the anx7625 node consumes it
> via a reference in "vdd33-supply"
> 
> [...]
> 
> > +	anx7625: encoder@58 {
> > +		compatible = "analogix,anx7625";
> > +		reg = <0x58>;
> > +		interrupts-extended = <&tlmm 81 IRQ_TYPE_EDGE_FALLING>;
> > +		vdd10-supply = <&pm4125_l11>;
> > +		vdd18-supply = <&pm4125_l15>;
> > +		vdd33-supply = <&vreg_anx_30>;
> > +		analogix,audio-enable;
> > +		analogix,lane0-swing = /bits/ 8 <0x14 0x54 0x64 0x74>;
> > +		analogix,lane1-swing = /bits/ 8 <0x14 0x54 0x64 0x74>;
> > +
> > +		pinctrl-0 = <&anx7625_int_pin>, <&anx7625_cable_det_pin>;
> 
> no mode-orientation/switch?

No, why? ANX handles everything internally.

> 
> 
> > +
> > +		connector {
> > +			compatible = "usb-c-connector";
> > +			power-role = "sink";
> > +			data-role = "dual";
> > +			try-power-role = "sink";
> > +
> > +			pd-revision = /bits/ 8 <0x03 0x00 0x00 0x00>;
> > +			op-sink-microwatt = <15000000>;
> > +			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
> > +				     PDO_VAR(5000, 20000, 3000)>;
> 
> nice!
> 
> > +
> > +			ports {
> > +				#address-cells = <1>;
> > +				#size-cells = <0>;
> > +
> > +				port@0 {
> > +					reg = <0>;
> 
> Please add a \n between the last prop and the following subnodes
> 
> lg otherwise
> 
> Konrad

-- 
With best wishes
Dmitry