Re: [PATCH v10 loongarch-next 2/3] LoongArch: Add 128-bit atomic cmpxchg support

[Thomas Weißschuh]

Hi!

On Sat, Jan 10, 2026 at 09:11:23PM +0800, George Guo wrote:
> From: George Guo <guodongtai@xxxxxxxxxx>
> 
> Implement 128-bit atomic compare-and-exchange using LoongArch's
> LL.D/SC.Q instructions.
> 
> At the same time, fix BPF scheduler test failures (scx_central scx_qmap)
> caused by kmalloc_nolock_noprof returning NULL due to missing
> 128-bit atomics. The NULL returns led to -ENOMEM errors during
> scheduler initialization, causing test cases to fail.
> 
> Verified by testing with the scx_qmap scheduler (located in
> tools/sched_ext/). Building with `make` and running
> ./tools/sched_ext/build/bin/scx_qmap.
> 
> Link: https://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf.git/commit/?id=5fb750e8a9ae
> Acked-by: Hengqi Chen <hengqi.chen@xxxxxxxxx>
> Tested-by: Hengqi Chen <hengqi.chen@xxxxxxxxx>
> Signed-off-by: George Guo <guodongtai@xxxxxxxxxx>

(...)

> +#define __arch_cmpxchg128(ptr, old, new)					\
> +({									\
> +	union __u128_halves __old, __new, __ret;			\
> +	volatile u64 *__ptr = (volatile u64 *)(ptr);			\
> +									\
> +	__old.full = (old);                                             \
> +	__new.full = (new);						\
> +									\
> +	__asm__ __volatile__(						\
> +	"1:   ll.d    %0, %3		# 128-bit cmpxchg low	\n"	\
> +	__WEAK_LLSC_MB							\
> +	"     ld.d    %1, %4		# 128-bit cmpxchg high	\n"	\
> +	"     bne     %0, %z5, 2f				\n"	\
> +	"     bne     %1, %z6, 2f				\n"	\
> +	"     move    $t0, %z7					\n"	\
> +	"     move    $t1, %z8					\n"	\
> +	"     sc.q    $t0, $t1, %2				\n"	\
> +	"     beqz    $t0, 1b					\n"	\
> +	"2:							\n"	\
> +	__WEAK_LLSC_MB							\
> +	: "=&r" (__ret.low), "=&r" (__ret.high)				\
> +	: "r" (__ptr),							\
> +	  "ZC" (__ptr[0]), "m" (__ptr[1]),				\
> +	  "Jr" (__old.low), "Jr" (__old.high),				\
> +	  "Jr" (__new.low), "Jr" (__new.high)				\
> +	: "t0", "t1", "memory");					\
> +									\
> +	__ret.full;							\
> +})

Older versions of binutils[0] seem to lack support for the sc.q instruction.
So there should be some validation of the toolchain capabilities.

ERROR:root:{standard input}: Assembler messages:
{standard input}:4831: Error: no match insn: sc.q	$t0,$t1,$r14
{standard input}:6407: Error: no match insn: sc.q	$t0,$t1,$r23
{standard input}:10856: Error: no match insn: sc.q	$t0,$t1,$r14
make[4]: *** [../scripts/Makefile.build:289: mm/slub.o] Error 1


[0] Tested with binutils 2.41 from the GCC 13.2 kernel.org toolchain.


Thomas