RE: [PATCH v2 06/10] pinctrl: renesas: rzg2l: Add support for RZ/G3L SoC
From: Biju Das
Date: Mon Feb 16 2026 - 05:37:45 EST
Hi All,
I have found some mistakes in the pinctrl tables during testing
after adding the pinctrl clone channel,i2c, display, audio, wdt,
rsci and rspi support.
> -----Original Message-----
> From: Biju <biju.das.au@xxxxxxxxx>
> Sent: 03 February 2026 13:10
> Subject: [PATCH v2 06/10] pinctrl: renesas: rzg2l: Add support for RZ/G3L SoC
>
> From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
>
> Add pinctrl driver support for RZ/G3L SoC.
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> ---
> v1->v2:
> * No change
> ---
> drivers/pinctrl/renesas/pinctrl-rzg2l.c | 228 ++++++++++++++++++++++++
> 1 file changed, 228 insertions(+)
>
> diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> index 5e3e56e32cea..e45282afcf86 100644
> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> @@ -26,6 +26,7 @@
> #include <linux/pinctrl/pinctrl.h>
> #include <linux/pinctrl/pinmux.h>
>
> +#include <dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h>
> #include <dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h>
> #include <dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h>
> #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
> @@ -93,6 +94,17 @@
>
> #define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | PIN_CFG_NF)
>
> +#define RZG3L_MPXED_ETH_PIN_FUNCS(ether) \
> + (PIN_CFG_IO_VMC_##ether | \
> + PIN_CFG_IOLH_C | \
PIN_CFG_PUPD is missing.
> + PIN_CFG_NF)
> +
> +#define RZG3L_MPXED_PIN_FUNCS(group) (RZG2L_MPXED_COMMON_PIN_FUNCS(group) | \
> + PIN_CFG_SOFT_PS)
> +
> +#define RZG3L_MPXED_PIN_FUNCS_POC(grp, poc) (RZG3L_MPXED_PIN_FUNCS(grp) | \
RZG3L_MPXED_PIN_FUNCS->RZG2L_MPXED_COMMON_PIN_FUNCS, so that driver sets the PoC register.
> + PIN_CFG_PVDD1833_OTH_##poc##_POC)
> +
> #define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(61, 54)
> #define PIN_CFG_PIN_REG_MASK GENMASK_ULL(53, 46)
> #define PIN_CFG_MASK GENMASK_ULL(31, 0)
> @@ -229,12 +241,14 @@ static const struct pin_config_item renesas_rzv2h_conf_items[] = {
> * @sd_ch: SD_CH register offset
> * @eth_poc: ETH_POC register offset
> * @oen: OEN register offset
> + * @other_poc: OTHER_POC register offset
> */
> struct rzg2l_register_offsets {
> u16 pwpr;
> u16 sd_ch;
> u16 eth_poc;
> u16 oen;
> + u16 other_poc;
> };
>
> /**
> @@ -333,6 +347,7 @@ struct rzg2l_pinctrl_pin_settings {
> * @smt: SMT registers cache
> * @sd_ch: SD_CH registers cache
> * @eth_poc: ET_POC registers cache
> + * @other_poc: OTHER_POC register cache
> * @oen: Output Enable register cache
> * @qspi: QSPI registers cache
> */
> @@ -348,6 +363,7 @@ struct rzg2l_pinctrl_reg_cache {
> u8 sd_ch[2];
> u8 eth_poc[2];
> u8 oen;
> + u8 other_poc;
> u8 qspi;
> };
>
> @@ -397,6 +413,60 @@ static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl,
> return 0;
> }
>
> +static const u64 r9a08g046_variable_pin_cfg[] = {
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 0, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0) | PIN_CFG_IEN),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 1, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 2, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 3, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 4, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 5, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 6, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0) | PIN_CFG_IEN),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 7, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 0, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 1, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0) | PIN_CFG_OEN),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 2, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 3, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 4, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 5, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 6, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 7, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 0, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1) | PIN_CFG_IEN),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 1, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 2, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 3, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 4, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 5, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 6, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 7, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 0, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 1, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1) | PIN_CFG_OEN),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 2, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 3, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 4, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 5, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 6, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 7, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 0, RZG3L_MPXED_PIN_FUNCS(B)),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 1, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 2, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 3, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 4, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 5, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 6, RZG3L_MPXED_PIN_FUNCS_POC(B, ISO)),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 7, RZG3L_MPXED_PIN_FUNCS_POC(B, ISO)),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 0, RZG3L_MPXED_PIN_FUNCS(B)),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 1, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 2, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 3, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 4, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 5, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 0, RZG3L_MPXED_PIN_FUNCS(A) | PIN_CFG_IEN),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 1, RZG3L_MPXED_PIN_FUNCS(A)),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 2, RZG3L_MPXED_PIN_FUNCS(A)),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 3, RZG3L_MPXED_PIN_FUNCS(A)),
> + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 4, RZG3L_MPXED_PIN_FUNCS(A)), };
> +
> static const u64 r9a09g047_variable_pin_cfg[] = {
> RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
> RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 1, RZV2H_MPXED_PIN_FUNCS), @@ -2141,6 +2211,70 @@ static
> const u64 r9a09g047_gpio_configs[] = {
> RZG2L_GPIO_PORT_PACK(4, 0x3c, RZV2H_MPXED_PIN_FUNCS), /* PS */
> };
>
> +static const char * const rzg3l_gpio_names[] = {
> + "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "",
> + "P20", "P21", "P22", "P23", "P24", "P25", "P26", "P27",
> + "P30", "P31", "P32", "P33", "P34", "P35", "P36", "P37",
> + "", "", "", "", "", "", "", "",
> + "P50", "P51", "P52", "P53", "P54", "P55", "P56", "P57",
> + "P60", "P61", "P62", "P63", "P64", "P65", "P66", "P67",
> + "P70", "P71", "P72", "P73", "P74", "P75", "P76", "P77",
> + "P80", "P81", "P82", "P83", "P84", "P85", "P86", "P87",
> + "", "", "", "", "", "", "", "",
> + "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7",
> + "PB0", "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7",
> + "PC0", "PC1", "PC2", "PC3", "PC4", "PC5", "PC6", "PC7",
> + "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
> + "PE0", "PE1", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7",
> + "PF0", "PF1", "PF2", "PF3", "PF4", "PF5", "PF6", "PF7",
> + "PG0", "PG1", "PG2", "PG3", "PG4", "PG5", "PG6", "PG7",
> + "PH0", "PH1", "PH2", "PH3", "PH4", "PH5", "PH6", "PH7",
> + "", "", "", "", "", "", "", "",
> + "PJ0", "PJ1", "PJ2", "PJ3", "PJ4", "PJ5", "PJ6", "PJ7",
> + "PK0", "PK1", "PK2", "PK3", "PK4", "PK5", "PK6", "PK7",
> + "PL0", "PL1", "PL2", "PL3", "PL4", "PL5", "PL6", "PL7",
> + "PM0", "PM1", "PM2", "PM3", "PM4", "PM5", "PM6", "PM7",
> + "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "",
> + "PS0", "PS1", "PS2", "PS3", "PS4", "PS5", "PS6", "PS7", };
> +
> +static const u64 r9a08g046_gpio_configs[] = {
> + 0x0,
> + 0x0,
> + RZG2L_GPIO_PORT_PACK(2, 0x22, PIN_CFG_NF | PIN_CFG_IEN), /* P2 */
> + RZG2L_GPIO_PORT_PACK(7, 0x23, RZG3L_MPXED_PIN_FUNCS_POC(A, AWO)), /* P3 */
> + 0x0,
> + RZG2L_GPIO_PORT_PACK(7, 0x25, RZG3L_MPXED_PIN_FUNCS_POC(A, AWO)), /* P5 */
> + RZG2L_GPIO_PORT_PACK(7, 0x26, RZG3L_MPXED_PIN_FUNCS_POC(A, AWO)), /* P6 */
> + RZG2L_GPIO_PORT_PACK(8, 0x27, RZG3L_MPXED_PIN_FUNCS_POC(A, AWO)), /* P7 */
> + RZG2L_GPIO_PORT_PACK(6, 0x28, RZG3L_MPXED_PIN_FUNCS_POC(A, AWO)), /* P8 */
P{5,6,7,8} IO domain is ISO.
> + 0x0,
> + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2a), /* PA */
> + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2b), /* PB */
> + RZG2L_GPIO_PORT_PACK(3, 0x2c, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), /* PC */
> + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2d), /* PD */
> + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2e), /* PE */
> + RZG2L_GPIO_PORT_PACK(3, 0x2f, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), /* PF */
> + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x30), /* PG */
> + RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x31), /* PH */
> + 0x0,
> + RZG2L_GPIO_PORT_PACK_VARIABLE(5, 0x33), /* PJ */
> + RZG2L_GPIO_PORT_PACK(4, 0x34, RZG3L_MPXED_PIN_FUNCS_POC(B, AWO)), /* PK */
AWO->ISO.
Cheers,
Biju