Re: [PATCH 12/13] serial: linflexuart: Add DMA support
From: kernel test robot
Date: Mon Feb 16 2026 - 22:27:36 EST
Hi Larisa,
kernel test robot noticed the following build warnings:
[auto build test WARNING on tty/tty-testing]
[also build test WARNING on tty/tty-next tty/tty-linus usb/usb-testing usb/usb-next usb/usb-linus robh/for-next linus/master v6.19 next-20260216]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Larisa-Grigore/serial-linflexuart-Fix-locking-in-set_termios/20260216-231403
base: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty.git tty-testing
patch link: https://lore.kernel.org/r/20260216150205.212318-13-larisa.grigore%40oss.nxp.com
patch subject: [PATCH 12/13] serial: linflexuart: Add DMA support
config: i386-buildonly-randconfig-002-20260217 (https://download.01.org/0day-ci/archive/20260217/202602171112.rMhRspEp-lkp@xxxxxxxxx/config)
compiler: clang version 20.1.8 (https://github.com/llvm/llvm-project 87f0227cb60147a26a1eeb4fb06e3b505e9c7261)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260217/202602171112.rMhRspEp-lkp@xxxxxxxxx/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@xxxxxxxxx>
| Closes: https://lore.kernel.org/oe-kbuild-all/202602171112.rMhRspEp-lkp@xxxxxxxxx/
All warnings (new ones prefixed by >>):
>> drivers/tty/serial/fsl_linflexuart.c:1095:6: warning: variable 'baud' is used uninitialized whenever 'if' condition is false [-Wsometimes-uninitialized]
1095 | if (port->uartclk) {
| ^~~~~~~~~~~~~
drivers/tty/serial/fsl_linflexuart.c:1113:67: note: uninitialized use occurs here
1113 | lfport->dma_rx_timeout = msecs_to_jiffies(DIV_ROUND_UP(10000000, baud));
| ^~~~
include/linux/math.h:49:22: note: expanded from macro 'DIV_ROUND_UP'
49 | #define DIV_ROUND_UP __KERNEL_DIV_ROUND_UP
| ^
include/uapi/linux/const.h:51:46: note: expanded from macro '__KERNEL_DIV_ROUND_UP'
51 | #define __KERNEL_DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
| ^
drivers/tty/serial/fsl_linflexuart.c:1095:2: note: remove the 'if' if its condition is always true
1095 | if (port->uartclk) {
| ^~~~~~~~~~~~~~~~~~
drivers/tty/serial/fsl_linflexuart.c:970:19: note: initialize the variable 'baud' to silence this warning
970 | unsigned int baud;
| ^
| = 0
drivers/tty/serial/fsl_linflexuart.c:205:13: warning: unused function 'linflex_console_putchar' [-Wunused-function]
205 | static void linflex_console_putchar(struct uart_port *port, unsigned char ch);
| ^~~~~~~~~~~~~~~~~~~~~~~
2 warnings generated.
vim +1095 drivers/tty/serial/fsl_linflexuart.c
1d3f5f07fafc712 Radu Pirea 2026-02-16 959
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 960 static void
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 961 linflex_set_termios(struct uart_port *port, struct ktermios *termios,
bec5b814d46c2a7 Ilpo Järvinen 2022-08-16 962 const struct ktermios *old)
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 963 {
0b34325c5f79f1f Larisa Grigore 2026-02-16 964 struct linflex_port *lfport = to_linflex_port(port);
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 965 unsigned long flags;
1312e6586227421 Larisa Grigore 2026-02-16 966 unsigned long cr, old_cr, cr1, gcr;
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 967 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1d3f5f07fafc712 Radu Pirea 2026-02-16 968 unsigned long ibr, fbr, divisr, dividr;
1d3f5f07fafc712 Radu Pirea 2026-02-16 969 unsigned char ldiv_mul;
1d3f5f07fafc712 Radu Pirea 2026-02-16 970 unsigned int baud;
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 971
a75137a58feb092 Radu Pirea 2026-02-16 972 uart_port_lock_irqsave(port, &flags);
a75137a58feb092 Radu Pirea 2026-02-16 973
0b34325c5f79f1f Larisa Grigore 2026-02-16 974 _linflex_stop_rx(port);
0b34325c5f79f1f Larisa Grigore 2026-02-16 975 _linflex_stop_tx(port);
0b34325c5f79f1f Larisa Grigore 2026-02-16 976
fb1da4d7f0bec28 Larisa Grigore 2026-02-16 977 old_cr = readl(port->membase + UARTCR) &
fb1da4d7f0bec28 Larisa Grigore 2026-02-16 978 ~(LINFLEXD_UARTCR_RXEN | LINFLEXD_UARTCR_TXEN);
fb1da4d7f0bec28 Larisa Grigore 2026-02-16 979 cr = old_cr;
fb1da4d7f0bec28 Larisa Grigore 2026-02-16 980
fb1da4d7f0bec28 Larisa Grigore 2026-02-16 981 /* In FIFO mode, we should make sure the fifo is empty
fb1da4d7f0bec28 Larisa Grigore 2026-02-16 982 * before entering INITM.
fb1da4d7f0bec28 Larisa Grigore 2026-02-16 983 */
fb1da4d7f0bec28 Larisa Grigore 2026-02-16 984 linflex_wait_tx_fifo_empty(port);
fb1da4d7f0bec28 Larisa Grigore 2026-02-16 985
fb1da4d7f0bec28 Larisa Grigore 2026-02-16 986 /* disable transmit and receive */
fb1da4d7f0bec28 Larisa Grigore 2026-02-16 987 writel(old_cr, port->membase + UARTCR);
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 988
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 989 /* Enter initialization mode by setting INIT bit */
5e8e1ccacae0470 Larisa Grigore 2026-02-16 990 cr1 = LINFLEXD_LINCR1_INIT | LINFLEXD_LINCR1_MME;
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 991 writel(cr1, port->membase + LINCR1);
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 992
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 993 /* wait for init mode entry */
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 994 while ((readl(port->membase + LINSR)
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 995 & LINFLEXD_LINSR_LINS_MASK)
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 996 != LINFLEXD_LINSR_LINS_INITMODE)
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 997 ;
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 998
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 999 /*
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1000 * only support CS8 and CS7, and for CS7 must enable PE.
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1001 * supported mode:
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1002 * - (7,e/o,1)
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1003 * - (8,n,1)
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1004 * - (8,e/o,1)
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1005 */
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1006 /* enter the UART into configuration mode */
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1007
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1008 while ((termios->c_cflag & CSIZE) != CS8 &&
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1009 (termios->c_cflag & CSIZE) != CS7) {
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1010 termios->c_cflag &= ~CSIZE;
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1011 termios->c_cflag |= old_csize;
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1012 old_csize = CS8;
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1013 }
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1014
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1015 if ((termios->c_cflag & CSIZE) == CS7) {
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1016 /* Word length: WL1WL0:00 */
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1017 cr = old_cr & ~LINFLEXD_UARTCR_WL1 & ~LINFLEXD_UARTCR_WL0;
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1018 }
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1019
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1020 if ((termios->c_cflag & CSIZE) == CS8) {
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1021 /* Word length: WL1WL0:01 */
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1022 cr = (old_cr | LINFLEXD_UARTCR_WL0) & ~LINFLEXD_UARTCR_WL1;
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1023 }
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1024
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1025 if (termios->c_cflag & CMSPAR) {
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1026 if ((termios->c_cflag & CSIZE) != CS8) {
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1027 termios->c_cflag &= ~CSIZE;
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1028 termios->c_cflag |= CS8;
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1029 }
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1030 /* has a space/sticky bit */
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1031 cr |= LINFLEXD_UARTCR_WL0;
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1032 }
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1033
1312e6586227421 Larisa Grigore 2026-02-16 1034 gcr = readl(port->membase + GCR);
1312e6586227421 Larisa Grigore 2026-02-16 1035
1312e6586227421 Larisa Grigore 2026-02-16 1036 if (termios->c_cflag & CSTOPB) {
1312e6586227421 Larisa Grigore 2026-02-16 1037 /* Use 2 stop bits. */
1312e6586227421 Larisa Grigore 2026-02-16 1038 cr = (cr & ~LINFLEXD_UARTCR_SBUR_MASK) |
1312e6586227421 Larisa Grigore 2026-02-16 1039 LINFLEXD_UARTCR_SBUR_2SBITS;
1312e6586227421 Larisa Grigore 2026-02-16 1040 /* Set STOP in GCR field for 2 stop bits. */
1312e6586227421 Larisa Grigore 2026-02-16 1041 gcr = (gcr & ~LINFLEXD_GCR_STOP_MASK) |
1312e6586227421 Larisa Grigore 2026-02-16 1042 LINFLEXD_GCR_STOP_2SBITS;
1312e6586227421 Larisa Grigore 2026-02-16 1043 } else {
1312e6586227421 Larisa Grigore 2026-02-16 1044 /* Use 1 stop bit. */
1312e6586227421 Larisa Grigore 2026-02-16 1045 cr = (cr & ~LINFLEXD_UARTCR_SBUR_MASK) |
1312e6586227421 Larisa Grigore 2026-02-16 1046 LINFLEXD_UARTCR_SBUR_1SBITS;
1312e6586227421 Larisa Grigore 2026-02-16 1047 /* Set STOP in GCR field for 1 stop bit. */
1312e6586227421 Larisa Grigore 2026-02-16 1048 gcr = (gcr & ~LINFLEXD_GCR_STOP_MASK) |
1312e6586227421 Larisa Grigore 2026-02-16 1049 LINFLEXD_GCR_STOP_1SBITS;
1312e6586227421 Larisa Grigore 2026-02-16 1050 }
1312e6586227421 Larisa Grigore 2026-02-16 1051 /* Update GCR register. */
1312e6586227421 Larisa Grigore 2026-02-16 1052 writel(gcr, port->membase + GCR);
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1053
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1054 /* parity must be enabled when CS7 to match 8-bits format */
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1055 if ((termios->c_cflag & CSIZE) == CS7)
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1056 termios->c_cflag |= PARENB;
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1057
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1058 if ((termios->c_cflag & PARENB)) {
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1059 cr |= LINFLEXD_UARTCR_PCE;
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1060 if (termios->c_cflag & PARODD)
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1061 cr = (cr | LINFLEXD_UARTCR_PC0) &
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1062 (~LINFLEXD_UARTCR_PC1);
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1063 else
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1064 cr = cr & (~LINFLEXD_UARTCR_PC1 &
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1065 ~LINFLEXD_UARTCR_PC0);
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1066 } else {
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1067 cr &= ~LINFLEXD_UARTCR_PCE;
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1068 }
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1069
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1070 port->read_status_mask = 0;
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1071
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1072 if (termios->c_iflag & INPCK)
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1073 port->read_status_mask |= (LINFLEXD_UARTSR_FEF |
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1074 LINFLEXD_UARTSR_PE0 |
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1075 LINFLEXD_UARTSR_PE1 |
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1076 LINFLEXD_UARTSR_PE2 |
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1077 LINFLEXD_UARTSR_PE3);
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1078 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1079 port->read_status_mask |= LINFLEXD_UARTSR_FEF;
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1080
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1081 /* characters to ignore */
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1082 port->ignore_status_mask = 0;
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1083 if (termios->c_iflag & IGNPAR)
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1084 port->ignore_status_mask |= LINFLEXD_UARTSR_PE;
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1085 if (termios->c_iflag & IGNBRK) {
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1086 port->ignore_status_mask |= LINFLEXD_UARTSR_PE;
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1087 /*
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1088 * if we're ignoring parity and break indicators,
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1089 * ignore overruns too (for real raw support).
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1090 */
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1091 if (termios->c_iflag & IGNPAR)
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1092 port->ignore_status_mask |= LINFLEXD_UARTSR_BOF;
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1093 }
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1094
1d3f5f07fafc712 Radu Pirea 2026-02-16 @1095 if (port->uartclk) {
1d3f5f07fafc712 Radu Pirea 2026-02-16 1096 ldiv_mul = linflex_ldiv_multiplier(port);
1d3f5f07fafc712 Radu Pirea 2026-02-16 1097 baud = uart_get_baud_rate(port, termios, old, 0,
1d3f5f07fafc712 Radu Pirea 2026-02-16 1098 port->uartclk / ldiv_mul);
1d3f5f07fafc712 Radu Pirea 2026-02-16 1099
1d3f5f07fafc712 Radu Pirea 2026-02-16 1100 /* update the per-port timeout */
1d3f5f07fafc712 Radu Pirea 2026-02-16 1101 uart_update_timeout(port, termios->c_cflag, baud);
1d3f5f07fafc712 Radu Pirea 2026-02-16 1102
1d3f5f07fafc712 Radu Pirea 2026-02-16 1103 divisr = port->uartclk;
1d3f5f07fafc712 Radu Pirea 2026-02-16 1104 dividr = ((unsigned long)baud * ldiv_mul);
1d3f5f07fafc712 Radu Pirea 2026-02-16 1105
1d3f5f07fafc712 Radu Pirea 2026-02-16 1106 ibr = divisr / dividr;
1d3f5f07fafc712 Radu Pirea 2026-02-16 1107 fbr = ((divisr % dividr) * 16 / dividr) & 0xF;
1d3f5f07fafc712 Radu Pirea 2026-02-16 1108
1d3f5f07fafc712 Radu Pirea 2026-02-16 1109 writel(ibr, port->membase + LINIBRR);
1d3f5f07fafc712 Radu Pirea 2026-02-16 1110 writel(fbr, port->membase + LINFBRR);
1d3f5f07fafc712 Radu Pirea 2026-02-16 1111 }
1d3f5f07fafc712 Radu Pirea 2026-02-16 1112
0b34325c5f79f1f Larisa Grigore 2026-02-16 1113 lfport->dma_rx_timeout = msecs_to_jiffies(DIV_ROUND_UP(10000000, baud));
0b34325c5f79f1f Larisa Grigore 2026-02-16 1114
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1115 writel(cr, port->membase + UARTCR);
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1116
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1117 cr1 &= ~(LINFLEXD_LINCR1_INIT);
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1118
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1119 writel(cr1, port->membase + LINCR1);
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1120
fb1da4d7f0bec28 Larisa Grigore 2026-02-16 1121 cr |= (LINFLEXD_UARTCR_TXEN) | (LINFLEXD_UARTCR_RXEN);
fb1da4d7f0bec28 Larisa Grigore 2026-02-16 1122 writel(cr, port->membase + UARTCR);
fb1da4d7f0bec28 Larisa Grigore 2026-02-16 1123
0b34325c5f79f1f Larisa Grigore 2026-02-16 1124 _linflex_start_rx(port);
0b34325c5f79f1f Larisa Grigore 2026-02-16 1125 _linflex_start_tx(port);
0b34325c5f79f1f Larisa Grigore 2026-02-16 1126
7c6725ffd581335 Thomas Gleixner 2023-09-14 1127 uart_port_unlock_irqrestore(port, flags);
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1128 }
09864c1cdf5c537 Stefan-gabriel Mirea 2019-08-09 1129
--
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