[PATCH v4 3/3] arm64: dts: qcom: monaco: enable the inline crypto engine for SDHC
From: Neeraj Soni
Date: Tue Feb 17 2026 - 00:26:22 EST
Add an ICE node to monaco SoC description and enable it by adding a
phandle to the SDHC node.
---
arch/arm64/boot/dts/qcom/monaco.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
index 816fa2af8a9a..365af78b01ae 100644
--- a/arch/arm64/boot/dts/qcom/monaco.dtsi
+++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
@@ -4202,6 +4202,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
supports-cqe;
dma-coherent;
+ qcom,ice = <&sdhc_ice>;
+
status = "disabled";
sdhc1_opp_table: opp-table {
@@ -4229,6 +4231,13 @@ opp-384000000 {
};
};
+ sdhc_ice: crypto@87c8000 {
+ compatible = "qcom,qcs8300-inline-crypto-engine",
+ "qcom,inline-crypto-engine";
+ reg = <0x0 0x087c8000 0x0 0x18000>;
+ clocks = <&gcc GCC_SDCC1_ICE_CORE_CLK>;
+ };
+
usb_1_hsphy: phy@8904000 {
compatible = "qcom,qcs8300-usb-hs-phy",
"qcom,usb-snps-hs-7nm-phy";
--
2.34.1