Re: [PATCH v6 1/2] arm64: dts: qcom: qcs8300: add Display Serial Interface device nodes
From: Ayushi Makhija
Date: Tue Feb 17 2026 - 00:27:52 EST
On 2/12/2026 3:57 PM, Loic Poulain wrote:
> Hi Ayushi,
>
> On Sat, Jan 24, 2026 at 9:39 PM Ayushi Makhija
> <quic_amakhija@xxxxxxxxxxx> wrote:
>>
>> Add device tree nodes for the DSI0 controller with their corresponding
>> PHY found on Qualcomm QCS8300 SoC.
>>
>> Signed-off-by: Ayushi Makhija <quic_amakhija@xxxxxxxxxxx>
>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxxxxxxxx>
>> Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx>
>> ---
>> arch/arm64/boot/dts/qcom/monaco.dtsi | 105 ++++++++++++++++++++++++++-
>> 1 file changed, 104 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
>> index 5d2df4305d1c..7dda05bda3e7 100644
>> --- a/arch/arm64/boot/dts/qcom/monaco.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
>> @@ -3,6 +3,7 @@
>> * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
>> */
>>
>> +#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
>> #include <dt-bindings/clock/qcom,qcs8300-gcc.h>
>> #include <dt-bindings/clock/qcom,rpmh.h>
>> #include <dt-bindings/clock/qcom,sa8775p-camcc.h>
>> @@ -5573,9 +5574,19 @@ port@0 {
>> reg = <0>;
>>
>> dpu_intf0_out: endpoint {
>> +
>> remote-endpoint = <&mdss_dp0_in>;
>> };
>> };
>> +
>> + port@1 {
>> + reg = <1>;
>> +
>> + dpu_intf1_out: endpoint {
>> +
>> + remote-endpoint = <&mdss_dsi0_in>;
>> + };
>> + };
>> };
>>
>> mdp_opp_table: opp-table {
>> @@ -5603,6 +5614,96 @@ opp-650000000 {
>> };
>> };
>>
>> + mdss_dsi0: dsi@ae94000 {
>> + compatible = "qcom,qcs8300-dsi-ctrl",
>> + "qcom,sa8775p-dsi-ctrl",
>> + "qcom,mdss-dsi-ctrl";
>> + reg = <0x0 0x0ae94000 0x0 0x400>;
>> + reg-names = "dsi_ctrl";
>> +
>> + interrupt-parent = <&mdss>;
>> + interrupts = <4>;
>> +
>> + clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK>,
>> + <&dispcc MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK>,
>> + <&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK>,
>> + <&dispcc MDSS_DISP_CC_MDSS_ESC0_CLK>,
>> + <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
>> + <&gcc GCC_DISP_HF_AXI_CLK>;
>> + clock-names = "byte",
>> + "byte_intf",
>> + "pixel",
>> + "core",
>> + "iface",
>> + "bus";
>> +
>> + assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC>,
>> + <&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC>;
>> + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
>> + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
>> +
>> + phys = <&mdss_dsi0_phy>;
>
> I'm quite sure DSI requires a refgen regulator, so add the proper
> refgen-supply link.
>
Hi Loic, sure will add in new patchset.
Thanks,
Ayushi