[RFC PATCH 1/3] PCI: Add PCIe Gen 7 (128 GT/s) register and speed definitions
From: Ionut Nechita (Sunlight Linux)
Date: Tue Feb 17 2026 - 03:01:37 EST
From: Ionut Nechita <ionut_n2001@xxxxxxxxx>
Add register definitions for PCIe Gen 7 128 GT/s link speed:
- PCI_EXP_LNKCAP_SLS_128_0GB (encoding 0x7)
- PCI_EXP_LNKCAP2_SLS_128_0GB (bit 6 in Supported Link Speeds Vector)
- PCI_EXP_LNKCTL2_TLS_128_0GT (Target Link Speed 0x7)
- PCIE_SPEED_128_0GT enum value (0x1a)
Widen pci_dev.supported_speeds from u8 to u16 to accommodate the
expanded Supported Link Speeds Vector which now uses bits 1-7.
PCIe Gen 7 doubles the data rate to 128 GT/s using PAM4 signaling
with mandatory Flit mode encoding (1:1, no overhead), providing
up to 256 GB/s unidirectional (512 GB/s bi-directional) bandwidth
on an x16 link.
Note: Based on the PCIe 7.0 specification announced by PCI-SIG in
2022, targeted for member release in 2025. No hardware exists yet
to validate these definitions.
Signed-off-by: Ionut Nechita <ionut_n2001@xxxxxxxxx>
---
include/linux/pci.h | 3 ++-
include/uapi/linux/pci_regs.h | 3 +++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/include/linux/pci.h b/include/linux/pci.h
index b5cc0c2b99065..21dd6ea5beb6d 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -303,6 +303,7 @@ enum pci_bus_speed {
PCIE_SPEED_16_0GT = 0x17,
PCIE_SPEED_32_0GT = 0x18,
PCIE_SPEED_64_0GT = 0x19,
+ PCIE_SPEED_128_0GT = 0x1a,
PCI_SPEED_UNKNOWN = 0xff,
};
@@ -558,7 +559,7 @@ struct pci_dev {
struct pci_tsm *tsm; /* TSM operation state */
#endif
u16 acs_cap; /* ACS Capability offset */
- u8 supported_speeds; /* Supported Link Speeds Vector */
+ u16 supported_speeds; /* Supported Link Speeds Vector */
phys_addr_t rom; /* Physical address if not from BAR */
size_t romlen; /* Length if not from BAR */
/*
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 3add74ae25948..fa00c6ca9f382 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -545,6 +545,7 @@
#define PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */
#define PCI_EXP_LNKCAP_SLS_32_0GB 0x00000005 /* LNKCAP2 SLS Vector bit 4 */
#define PCI_EXP_LNKCAP_SLS_64_0GB 0x00000006 /* LNKCAP2 SLS Vector bit 5 */
+#define PCI_EXP_LNKCAP_SLS_128_0GB 0x00000007 /* LNKCAP2 SLS Vector bit 6 */
#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */
#define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */
#define PCI_EXP_LNKCAP_ASPM_L0S 0x00000400 /* ASPM L0s Support */
@@ -693,6 +694,7 @@
#define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */
#define PCI_EXP_LNKCAP2_SLS_32_0GB 0x00000020 /* Supported Speed 32GT/s */
#define PCI_EXP_LNKCAP2_SLS_64_0GB 0x00000040 /* Supported Speed 64GT/s */
+#define PCI_EXP_LNKCAP2_SLS_128_0GB 0x00000080 /* Supported Speed 128GT/s */
#define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */
#define PCI_EXP_LNKCTL2 0x30 /* Link Control 2 */
#define PCI_EXP_LNKCTL2_TLS 0x000f
@@ -702,6 +704,7 @@
#define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */
#define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */
#define PCI_EXP_LNKCTL2_TLS_64_0GT 0x0006 /* Supported Speed 64GT/s */
+#define PCI_EXP_LNKCTL2_TLS_128_0GT 0x0007 /* Supported Speed 128GT/s */
#define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */
#define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */
#define PCI_EXP_LNKCTL2_HASD 0x0020 /* HW Autonomous Speed Disable */
--
2.53.0