RE: [PATCH v3 06/10] clk: renesas: Add support for RZ/G3L SoC

[Biju Das]

Hi All,

> -----Original Message-----
> From: Biju <biju.das.au@xxxxxxxxx>
> Sent: 03 February 2026 10:30
> Subject: [PATCH v3 06/10] clk: renesas: Add support for RZ/G3L SoC
> 
> From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> 
> The clock structure for RZ/G3L is almost identical to RZ/G3S SoC with more IP blocks such as LCDC,
> CRU, LVDS and GPU.
> 
> Add minimal clock and reset entries required to boot the system on Renesas RZ/G3L SMARC EVK and binds
> it with the RZ/G2L CPG core driver.
> 
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> ---
> v2->v3:
>  * No change.
> v1->v2:
>  * Added CLK_ETH{0,1}_TXC_TX_CLK_IN and CLK_ETH{0,1}_RXC_RX_CLK_IN clocks.
>  * Dropped R9A08G046_IA55_PCLK from critical clock list.
> ---
>  drivers/clk/renesas/Kconfig         |   7 +-
>  drivers/clk/renesas/Makefile        |   1 +
>  drivers/clk/renesas/r9a08g046-cpg.c | 144 ++++++++++++++++++++++++++++
>  drivers/clk/renesas/rzg2l-cpg.c     |   6 ++
>  drivers/clk/renesas/rzg2l-cpg.h     |   1 +
>  5 files changed, 158 insertions(+), 1 deletion(-)  create mode 100644 drivers/clk/renesas/r9a08g046-
> cpg.c
> 
> diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index
> 6a5a04664990..0203ecbb3882 100644
> --- a/drivers/clk/renesas/Kconfig
> +++ b/drivers/clk/renesas/Kconfig
> @@ -39,6 +39,7 @@ config CLK_RENESAS
>  	select CLK_R9A07G044 if ARCH_R9A07G044
>  	select CLK_R9A07G054 if ARCH_R9A07G054
>  	select CLK_R9A08G045 if ARCH_R9A08G045
> +	select CLK_R9A08G046 if ARCH_R9A08G046
>  	select CLK_R9A09G011 if ARCH_R9A09G011
>  	select CLK_R9A09G047 if ARCH_R9A09G047
>  	select CLK_R9A09G056 if ARCH_R9A09G056 @@ -194,6 +195,10 @@ config CLK_R9A08G045
>  	bool "RZ/G3S clock support" if COMPILE_TEST
>  	select CLK_RZG2L
> 
> +config CLK_R9A08G046
> +	bool "RZ/G3L clock support" if COMPILE_TEST
> +	select CLK_RZG2L
> +
>  config CLK_R9A09G011
>  	bool "RZ/V2M clock support" if COMPILE_TEST
>  	select CLK_RZG2L
> @@ -250,7 +255,7 @@ config CLK_RCAR_USB2_CLOCK_SEL
>  	  This is a driver for R-Car USB2 clock selector
> 
>  config CLK_RZG2L
> -	bool "RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST
> +	bool "RZ/{G2{L,UL},G3{S,L},V2L} family clock support" if COMPILE_TEST
>  	select RESET_CONTROLLER
> 
>  config CLK_RZV2H
> diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index
> d28eb276a153..bd2bed91ab29 100644
> --- a/drivers/clk/renesas/Makefile
> +++ b/drivers/clk/renesas/Makefile
> @@ -36,6 +36,7 @@ obj-$(CONFIG_CLK_R9A07G043)		+= r9a07g043-cpg.o
>  obj-$(CONFIG_CLK_R9A07G044)		+= r9a07g044-cpg.o
>  obj-$(CONFIG_CLK_R9A07G054)		+= r9a07g044-cpg.o
>  obj-$(CONFIG_CLK_R9A08G045)		+= r9a08g045-cpg.o
> +obj-$(CONFIG_CLK_R9A08G046)		+= r9a08g046-cpg.o
>  obj-$(CONFIG_CLK_R9A09G011)		+= r9a09g011-cpg.o
>  obj-$(CONFIG_CLK_R9A09G047)		+= r9a09g047-cpg.o
>  obj-$(CONFIG_CLK_R9A09G056)		+= r9a09g056-cpg.o
> diff --git a/drivers/clk/renesas/r9a08g046-cpg.c b/drivers/clk/renesas/r9a08g046-cpg.c
> new file mode 100644
> index 000000000000..d77934872cf4
> --- /dev/null
> +++ b/drivers/clk/renesas/r9a08g046-cpg.c
> @@ -0,0 +1,144 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * RZ/G3L CPG driver
> + *
> + * Copyright (C) 2026 Renesas Electronics Corp.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/device.h>
> +#include <linux/init.h>
> +#include <linux/kernel.h>
> +
> +#include <dt-bindings/clock/r9a08g046-cpg.h>
> +
> +#include "rzg2l-cpg.h"
> +
> +/* RZ/G3L Specific registers. */
> +#define G3L_CPG_PL2_DDIV		(0x204)
> +#define G3L_CPG_PL3_DDIV		(0x208)
> +#define G3L_CLKDIVSTATUS		(0x280)
> +
> +/* RZ/G3L Specific division configuration.  */
> +#define G3L_DIVPL2A		DDIV_PACK(G3L_CPG_PL2_DDIV, 0, 2)
> +#define G3L_DIVPL2B		DDIV_PACK(G3L_CPG_PL2_DDIV, 4, 2)
> +#define G3L_DIVPL3A		DDIV_PACK(G3L_CPG_PL3_DDIV, 0, 2)
> +
> +/* RZ/G3L Clock status configuration. */
> +#define G3L_DIVPL2A_STS		DDIV_PACK(G3L_CLKDIVSTATUS, 4, 1)
> +#define G3L_DIVPL2B_STS		DDIV_PACK(G3L_CLKDIVSTATUS, 5, 1)
> +#define G3L_DIVPL3A_STS		DDIV_PACK(G3L_CLKDIVSTATUS, 8, 1)
> +
> +enum clk_ids {
> +	/* Core Clock Outputs exported to DT */
> +	LAST_DT_CORE_CLK = R9A08G046_CLK_P4_DIV2,
> +
> +	/* External Input Clocks */
> +	CLK_EXTAL,
> +	CLK_ETH0_TXC_TX_CLK_IN,
> +	CLK_ETH0_RXC_RX_CLK_IN,
> +	CLK_ETH1_TXC_TX_CLK_IN,
> +	CLK_ETH1_RXC_RX_CLK_IN,
> +
> +	/* Internal Core Clocks */
> +	CLK_PLL2,
> +	CLK_PLL2_DIV2,
> +	CLK_PLL3,
> +	CLK_PLL3_DIV2,
> +
> +	/* Module Clocks */
> +	MOD_CLK_BASE,
> +};
> +
> +/* Divider tables */
> +static const struct clk_div_table dtable_4_128[] = {
> +	{ 0, 4 },
> +	{ 1, 2 },

Typo 2->8

Cheers,
Biju